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“Standard”:
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA1756
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
This product is Dual N-Channel MOS Field Effect
Transistor designed for power management
application of notebook computers, and Li-ion
battery application.
PACKAGE DRAWING (Unit : mm)
8
5
1 ; Source 1
2 ; Gate 1
7, 8 ; Drain 1
3 ; Source 2
4 ; Gate 2
5, 6 ; Drain 2
1
4
5.37 Max.
+0.10
–0.05
FEATURES
•
Dual MOS FET chips in small package
•
2.5-V gate drive type and low on-resistance
R
DS(on)1
= 30 mΩ MAX. (V
GS
= 4.5 V, I
D
= 3.0 A)
R
DS(on)2
= 40 mΩ MAX. (V
GS
= 2.5 V, I
D
= 3.0 A)
•
Low C
iss
C
iss
= 800 pF TYP.
•
Built-in G-S protection diode
•
Small and surface mount package (Power SOP8)
6.0 ±0.3
4.4
0.8
1.8 Max.
1.44
0.15
0.05 Min.
0.5 ±0.2
0.10
1.27
0.40
0.78 Max.
0.12 M
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power SOP8
+0.10
–0.05
µ
PA1756G
ABSOLUTE MAXIMUM RATINGS (T
A
= 25 °C)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
Drain Current (Pulse)
Note1
Note2
Note2
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
P
T
T
ch
T
stg
20
±12.0
±6.0
±24
1.7
2.0
150
−55
to +150
V
V
A
A
W
W
°C
°C
EQUIVALENT CIRCUIT
Drain
Total Power Dissipation (1 unit)
Total Power Dissipation (2 unit)
Channel Temperature
Storage Temperature
Gate
Body
Diode
Gate
Protection
Diode
Source
Notes 1.
PW
≤
10
µ
s, Duty Cycle
≤
1 %
2
2.
T
A
= 25 °C, Mounted on ceramic substrate of 2000 mm x 1.1 mm
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD. When this
device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage
may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D12909EJ2V0DS00 (2nd edition)
Date Published May 2001 NS CP (K)
Printed in Japan
The mark
5
shows major revised points.
©
1999
FPGA/CPLD
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