4Mbit Mixed Technology Module
PUMA 2SF4006
Issue 5.1 May 2001
Description
The PUMA2SF4006 is a mixed technology ceramic
PGA module organised as 128K x 16 SRAM and
128K x 16 FLASH.
The PUMA2 has a industry standard footprint, the
device can be user configured as 8 or 16 bit wide.
High speed 5V FLASH and SRAM technology is
utilised. Access time of 70 to 120ns (FLASH) and 20
to 35ns (SRAM) are available.
The PUMA2SF4006 Module is available to
Commercial, Industrial or Military temperature
grades. A Military Screened option is also available.
Block Diagram
A0~A16
/OE
/WE4
/WE3
/WE2
/WE1
Site 1
Site 2
Site 3
Site 4
128K x 8
SRAM
/CS1
/CS2
/CS3
/CS4
D0~7
D8~15
D16~23
D24~31
128K x 8
SRAM
128K x 8
FLASH
128K x 8
FLASH
Features
• Mixed Technology 4 Mbit module
• 128K x 16 FLASH & 128K x 16 SRAM.
• User configurable as 8 or 16 Bits wide.
• Access times :- 20 to 35ns SRAM
70 to 120ns FLASH.
• 5V + 10% Supply Voltage.
• Industry standard footprint
• May be screened in accordance with :-
MIL-STD-883C
FLASH Data.
• 5V Program and Erase.
• 16 Kbyte Sector Size.
• Embedded Erase and Program Algorithm.
• 10, 000 W/E Cycle Endurance.
• 10 year Data Retention.
Pin Definition
See page 2.
Pin Functions
Description
Address Input
Data Input/Output
SRAM Chip Selects
FLASH Chip Selects
SRAM Write Enable
FLASH Write Enable
Output Enable
Power
Ground
Signal
A0~A16
D0~D31
/CS1~2
/CS3~4
/WE1~2
/WE3~4
/OE
V
CC
V
SS
Package Details
PUMA2 - Ceramic PGA
Max. Dimensions (mm) - 27.69 x 27.69 x 8.13
Pin Definition - PUMA2SF4006
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Signal
D8
D9
D10
A13
A14
A15
A16
NC
D0
D1
D2
/WE2
/CS2
V
SS
D11
A10
A11
A12
V
CC
/CS1
NC
D3
D15
D14
D13
D12
/OE
NC
/WE1
D7
D6
D5
D4
Pin
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Signal
D24
D25
D26
A6
A7
NC
A8
A9
D16
D17
D18
V
CC
/CS4
/WE4
D27
A3
A4
A5
/WE3
/CS3
V
SS
D19
D31
D30
D29
D28
A0
A1
A2
D23
D22
D21
D20
PAGE 2
Issue 5.1 May 2001
SRAM Section
Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin Relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
IN
/V
OUT
P
D
T
STG
-55
Min
-0.5
to
2.0
to
+150
Max
+7.0
Unit
V
W
O
DC Operating Conditions
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
(Commercial)
(Industrial)
(Military)
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
T
AM
Min
4.5
2.2
-0.5
0
-40
-55
Typ
5.0
-
-
-
-
-
Max
5.5
V
CC
+0.5
0.8
70
85
125
Unit
V
V
V
O
O
O
C
C
C
(Suffix I)
(Suffix M,MB)
DC Electrical Characteristics
(V
CC
=5V+10%, T
A
=-55
O
C to +125
O
C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Standby Current
(TTL)
(CMOS)
Output Voltage Low
Output Voltage High
Symbol Test Condition
I
LI
I
LO
I
CC
I
SB1
I
SB2
V
OL
V
OH
V
IN
= V
SS
to V
CC
/CS#=V
IH
or /OE=V
IH
or /WE=V
IL
,
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty /CS#=V
IL
,
V
IN
=V
IH
or V
IL
, I
OUT
=0mA
Min. Cycle, /CS#=V
IH
Min
-4
-4
-
-
-
-
2.4
Max
4
4
340
80
10
0.4
-
Unit
µ
A
µ
A
mA
mA
mA
V
V
f
=0MHz, /CS#
>
VCC-0.2V or VIN
<
0.2V
I
OL
=8.0mA
I
OH
=-4.0mA
Notes : Typical Values are at V
CC
=5.0V, T
A
=25
O
C and specified loading.
PAGE 3
Issue 5.1 May 2001
Capacitance
(V
CC
= 5.0V+10%, T
A
= 25
O
C)
Parameter
Input Capacitance
Input/Output Capacitance
Symbol
C
IN
C
I/O
Test Condition
V
IN
=0V
V
I/O
=0V
Min
-
-
Typ Max
-
-
15
15
Unit
pF
pF
Note : These Parameters are calculated not measured.
Test Conditions
•
•
•
•
•
Input pulse levels : 0V to 3.0V
Input rise and fall times : 3ns
Input and Output timing reference levels : 1.5V
Output Load : See Load Diagram.
V
CC
= 5V+10%
Output Load
I/O Pin
645Ω
1.76V
100pF
Operating Modes
The table below shows the logic inputs required to control the operating modes of each of the SRAM’s on
the module
Mode
Not Selected
Output Disable
Read
Write
/CS#
1
0
0
0
/OE
X
1
0
X
/WE#
X
1
1
0
V
CC
Current
I
SB1
,I
SB2
I
CC
I
CC
I
CC
I/O Pin
High Z
High Z
D
OUT
D
IN
Reference Cycle
Power Down
-
Read Cycle
Write Cycle
Legend : 1 = V
IH
0 = V
IL
X = Don’t Care
PAGE 4
Issue 5.1 May 2001
Read Cycle
AC Operating Conditions
020
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Output Valid
Chip Enable to Low Z Output
Output Enable to Low Z Output
Chip Disable to High Z Output
Output Disable to High Z Output
Output Hold from Address Change
025
35
Symbol Min Max Min Max Min Max Units
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
20
-
-
-
3
0
0
0
3
-
20
20
10
-
-
10
10
-
25
-
-
-
3
0
0
0
3
-
25
25
12
-
-
12
12
-
35
-
-
-
3
0
0
0
3
-
35
35
15
-
-
15
15
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
020
Parameter
Write Cycle Time
Chip Select to End of Write
Address SetupTime
Address Valid to End of Write
Write Pulse Width (/OE# High)
Write Recovery Time
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low Z
Write to Output High Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
*
t
DW
t
DH
t
OW
t
WHZ
025
35
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min Max Min Max Min Max
20
15
0
15
12
0
10
0
3
0
-
-
-
-
-
-
-
-
-
12
25
20
0
20
15
0
12
0
3
0
-
-
-
-
-
-
-
-
-
15
35
25
0
25
20
0
15
0
3
0
-
-
-
-
-
-
-
-
-
20
PAGE 5
Issue 5.1 May 2001
FPGA/CPLD
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