Integrated
Circuit
Systems, Inc.
ICS9148-60
Pentium/Pro
TM
System Clock Chip
General Description
The
ICS9148-60
is part of a reduced pin count two-chip clock
solution for designs using an Intel BX style chipset.
Companion SDRAM buffers are ICS9179-11 and 12.
There are two PLLs, with the first PLL capable of spread
spectrum operation. Spread spectrum typically reduces system
EMI by 8-10dB. The second PLL provides support for USB
(48MHz) and 24MHz requirements. CPU frequencies up to
100MHz are supported.
The I
2
C interface allows stop clock programming, frequency
selection, and spread spectrum operation to be programmed.
Clock outputs include two CPU (2.5V or 3.3V), seven PCI
(3.3V), one REF (3.3V), one IOAPIC (2.5V or 3.3V), one 48MHz,
and one selectable 48_24MHz.
Features
Generates system clocks for CPU, PCI, IOAPIC ,
14.314 MHz, 48 and 24MHz.
Supports single or dual processor systems
Skew from CPU (earlier) to PCI clock 1 to 4ns
Separate 2.5V and 3.3V supply pins
2.5V outputs: CPU, IOAPIC
3.3V outputs: PCI, REF
No power supply sequence requirements
28 pin SOIC and SSOP
Spread Spectrum operation optional for PLL1
CPU frequencies to 100MHz are supported.
Pin Configuration
Block Diagram
28 pin SOIC and SSOP
Power Groups
VDD = Supply for PLL core
VDD1 = REF0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = 48MHz
VDDL = CPUCLK (0:1)
VDDL1=IOAPIC
Ground Groups
GND = Ground Source Core
GND1 = REF0, X1, X2
GND2 = PCICLK_F, PCICLK (0:5)
GND3=48MHz
GNDL = CPUCLK (0:1)
Pentium is a trademark on Intel Corporation.
9148-60 Rev D 10/19/99
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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ICS9148-60
Pin Descriptions
PIN NUMBER
1
2
3
4
5, 6, 7, 8, 10, 11
6, 9
12
13
14
15
16
17
18
19
20
21, 22
23
24
25
26
27
28
PIN NAME
X1
X2
GND2
PCICLK_F
PCICLK (0:5)
VDD2
VDD3
48MHz
24_48MHz
GND3
SEL100/66.6#
SCLK
SDATA
GND
VDD
CPUCLK (1:0)
VDDL
IOAPIC
VDDL
VDD1
REF0
SEL48#
GND1
TYPE
IN
OUT
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
IN
IN
IN
PWR
PWR
OUT
PWR
OUT
PWR
PWR
OUT
IN
PWR
DESCRIPTION
XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap
and feed back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Poer for 48MHz
Fixed CLK output @ 48MHz
Fixed CLK output; 24MHz if pin 27 =1 at power up, 48MHz if
pin 27=0 at power up.
Ground for 48MHz
Select pin for enabling 100MHz or 66.6MHz
H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz)
Clock input for I
2
C input
Data input for I
2
C input
Ground for CPUCLK (0:1)
Power for PLL core
CPU and Host clock outputs nominally 2.5V
Power for CPU outputs, nominally 2.5V
IOAPIC clock output 14.318MHz.
Power for IOAPIC
Power for REF outputs.
14.318MHz clock .
Output/Latched input at power up. When low, pin 14 is 48MHz
Ground for REF outputs, X1, X2.
2
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ICS9148-60
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will
acknowledge
each byte
one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
ICS (Slave/Receiver)
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Read:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
3
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ICS9148-60
Serial Bitmap
Byte 3: Functionality & Frequency Select
& Spread Slect Register
Bit
Description
0: Center Spread (±0.25)
7
1: Down Spread (0 to -0.6%)
Bit
CPU
PCI
654
34.25
68.5
000
37.5
75.0
001
41.6
83.3
010
6:4
33.3
66.6
011
34.3
103
100
37.3
112
101
44.43
133.3
110
33.33
100
111
0 - Frequency is selected by
3
hardware select SEL100/66.6#
1 - Frequency is selected by 6:4 above
2
(Reserved)
00 - Normal operation
01 - Test mode
10
10 - Spread sprectrum ON
11 - Tristate all outputs
PWD
0
Byte 5:
Bit
7
6
5
Pin#
4
11
10
-
8
7
6
5
Pin Name
PCICLK_F
PCICLK5
PCICLK4
-
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PWD
1
1
1
0
1
1
1
1
Description
Bit Value = 0 Bit Value = 1
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Disabled
Enabled
(low)
(Reserved)
(Reserved)
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Disabled
Enabled
(low)
0
4
3
2
0
1
0
Notes:
1 = Enabled; 0 = Disabled, outputs held low
00
Notes:
1 = Enabled; 0 = Disabled, outputs held low
Byte 4:
Bit
7
6
5
4
3
2
1
0
Pin#
-
-
-
-
-
21
-
22
Pin Name
-
-
-
-
-
CPUCLK1
-
CPUCLK0
PWD
-
-
-
-
-
1
0
1
Description
Bit Value = 0 Bit Value = 1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Disabled
Enabled
(low)
(Reserved)
(Reserved)
(Disabled)
Enabled
(low)
Byte 6:
Bit
7
6
5
4
3
2
1
0
Pin#
-
-
24
-
-
-
27
27
Pin Name
-
-
IOAPIC
-
-
-
REF0
REF0
PWD
0
0
1
0
0
0
1
1
Description
Bit Value = 0 Bit Value = 1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Disabled
Enabled
(low)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Disabled)
Enabled
(low)
(Disabled)
Enabled
(low)
Notes:
1 = Enabled; 0 = Disabled, outputs held low
Note:
PWD = Power-Up Default
Notes:
1 = Enabled; 0 = Disabled, outputs held low
For pin 27, there are 2 output stages together for 1 pin. These 2
latches must be both 0 or 1 simultaneously or there will be a short to
ground if one is disabled and the other is running.
4
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ICS9148-60
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . .
7.0 V
GND 0.5 V to V
DD
+0.5 V
0°C to +70°C
65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= V
DDL
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Power Down Supply
Current
Input frequency
Input Capacitance
1
Transition Time
1
Settling Time
1
Clk Stabilization
1
Skew
1
1
SYMBOL
V
IH
V
IL
I
IH
I
IL1
I
IL2
I
DD3.3OP66
I
DD3.3OP100
I
DD3.3PD
F
i
C
IN
C
INX
T
trans
T
s
T
STAB
T
AGP-PCI1
CONDITIONS
MIN
2
V
SS
-0.3
TYP
MAX
V
DD
+0.3
0.8
5
UNITS
V
V
µA
µA
µA
mA
mA
µ
A
MHz
pF
pF
ms
ms
ms
ns
V
IN
= V
DD
V
IN
= 0 V; Inputs with no pull-up resistors
V
IN
= 0 V; Inputs with pull-up resistors
C
L
= 0 pF; Select @ 66MHz
C
L
= 0 pF; Select @ 100MHz
C
L
= 0 pF; With input address to Vdd or GND
V
DD
= 3.3 V;
Logic Inputs
X1 & X2 pins
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From V
DD
= 3.3 V to 1% target Freq.
V
T
= 1.5 V;
-5
-200
0.1
2.0
-100
60
66
3
14.318
170
170
650
27
36
5
5
45
3
3
4
1
3.5
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
Supply Current
Power Down
Supply Current
Skew
1
1
SYMBOL
I
DD2.5OP 66
I
DD2.5OP 100
I
DD2.5PD
t
CP U-AGP
t
CP U-P CI2
CONDITIONS
C
L
= 0 pF; Select @ 66.8 MHz
C
L
= 0 pF; Select @ 100 MHz
C
L
= 0 pF; With input address to Vdd or GND
V
T
= 1.5 V; V
TL
= 1.25 V
MIN
TYP
16
23
10
MAX
72
100
100
1
4
UNITS
mA
mA
µA
ns
ns
0
1
0.5
2.6
Guaranteed by design, not 100% tested in production.
5
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