DATA SHEET
SKY73121-11: 1805–1890 MHz High Performance
VCO/Synthesizer With Integrated Switch
Applications
2G, 2.5G, and 3G base station transceivers:
GSM, EDGE, CDMA, WCDMA
General purpose RF systems
Description
Skyworks SKY73121-11 Voltage-Controlled Oscillator
(VCO)/Synthesizer is a fully integrated, high performance signal
source for high dynamic range transceivers. The device provides
ultra-fine frequency resolution, fast switching speed, and low
phase noise performance for 2G, 2.5G, and 3G base station
transceivers.
The SKY73121-11 VCO/Synthesizer is a key building block for
high-performance radio system designs that require low power
and a fine step size. Reference clock generators with an output
frequency up to 52 MHz can be used with the SKY73121-11. A
functional block diagram is shown in Figure 1. As indicated in this
diagram, the reference frequency is divided down by 1, 2, 4, or 8
in the R1 divider, depending on the value of the reference divisor
input (R1). Refer to the Reference Input Divider section (page 10)
for more information.
The SKY73121-11 VCO/Synthesizer is provided in a compact,
38-pin Multi-Chip Module (MCM). The device package and pinout
are shown in Figure 2. Signal pin assignments and functional pin
descriptions are provided in Table 1.
Features
Frequency operation range: 1805 to 1890 MHz
Process-tolerant compensation for VCO
24-bit
fractional-N synthesizer
Ultra-fine frequency resolution of 0.001 ppm
Flexible reference frequency selection
Three-wire serial interface up to 20 MHz clock frequency
Integrated PLL supply regulation for spur isolation
MCM (38-pin, 9 x 12 mm) SMT package (MSL3, 260 C per
JEDEC J-STD-020)
Varactor
Vtune
Lr
Cal
Lr
2
2
2
Buffer
VCO Out +
VCO Out –
Z = 1:4
RF Output
SW_EN
SR Out +
7
2
SR Out –
Vtune
cap
[6:0]
Flag
PLL
Low Pass Filter
3-Wire
Serial
Interface
CLK
LE
DAT
R1
SP1
SC1
CPO RF
FREF
R1
Divider
RF
PFD
RF Charge
Pump
N
PS
RF
IN
7
Mux
(LD/Test)
N
Divider
FN
ME
Divide-by-2
P/P+1
Prescaler
RF
INB
LD
ΔΣ
Modulator
Digital
Coarse
Calibration
cap
[6:0]
7
Calibration
Complete
S1040
Figure 1. SKY73121-11 Functional Block Diagram
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
200888B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 1, 2009
1
DATA SHEET • SKY73121-11 VCO/SYNTHESIZER
GND
GND
GND
GND
GND
GND
31
38
37
36
35
34
33
32
30
29
28
27
26
25
24
23
22
21
20
GND
GND
GND
SW_EN
GND
GND
GND
GND
GND
RF_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
GND
GND
N/C
GND
GND
GND
FREF
LD
N/C
GND
19
VDD
GND
GND
GND
N/C
GND
GND
N/C
DATA
CLK
LE
S958
Figure 2. SKY73121-11 Pinout– 38-Pin MCM Package
(Top View)
Table 1. SKY73121-11 Signal Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
GND
GND
GND
SW_EN
GND
GND
GND
GND
GND
RF_OUT
GND
GND
GND
N/C
GND
GND
CLK
DATA
LE
Name
Ground
Ground
Ground
Synthesizer RF output switch enable
Ground
Ground
Ground
Ground
Ground
Synthesizer output
Ground
Ground
Ground
No connection
Ground
Ground
Serial port clock
Serial port data
Serial port latch enable
Description
Pin #
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
GND
N/C
LD
FREF
GND
GND
GND
N/C
GND
GND
GND
GND
GND
N/C
GND
GND
GND
VDD
GND
Name
Ground
No connection
Lock detect output
Frequency reference input
Ground
Ground
Ground
No connection
Ground
Ground
Ground
Ground
Ground
No connection
Ground
Ground
Ground
+5 V power supply
Ground
Description
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
2
December 1, 2009 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200888B
DATA SHEET • SKY73121-11 VCO/SYNTHESIZER
Technical Description
The SKY73121-11 is a fractional-N frequency synthesizer using a
modulation technique. The fractional-N implementation
provides low in-band noise by having a low division and fast
frequency settling time. The device also provides programmable,
arbitrary fine frequency resolution. This compensates the
frequency synthesizer for crystal frequency drift.
Serial I/O Control Interface
The SKY73121-11 is programmed through a three-wire serial bus
control interface using four 26-bit words. The three-wire interface
consists of three signals: CLK (pin 17), LE (pin 19), and the bit
serial data line DATA (pin 18). The convention is to load data from
the most significant bit to the least significant bit (MSB to LSB). A
serial data input timing diagram is shown in Figure 3. Preset
timing parameter values are provided in Table 2.
Although the SKY73121-11 uses a 5 V DC supply, the internal
voltage regulator has a 3.3 V output for the PLL. Therefore, the
input DC voltage for the serial interface (CLK, DATA, and LE
signals) should be set to 3.3 V or lower.
Figure 4 depicts the serial bus, which consists of one 26-bit load
register and four separate 24-bit registers. Data is initially clocked
into the load register starting with the MSB and ending with the
LSB. The LE signal is used to gate the clock to the load register,
requiring the LE signal to be brought low before the data load.
Data is shifted on the rising edge of CLK.
The two final LSBs are decoded to determine which holding
register should latch the data. The falling edge of LE latches the
data into the appropriate holding register. This programming
sequence must be repeated to fill all four holding registers.
The specific hold register addresses are determined by the wd_0
and wd_1 parameters in the load register. These are the two
LSBs (bits [1:0]) as shown in Figure 4. Table 3 lists the four hold
registers and their respective addresses as determined in the load
register.
The contents of each word in the load register are used to
program the four hold registers described in Tables 4 through 7.
The dpll_ctrl parameter (bits [19:2] of Word 1) programs the
Digital Phase Locked Loop (DPLL) block. Each of the 18 bits that
comprise the dpll_ctrl parameter map directly to the signal ports
on the DPLL block as shown in Table 8 (except for the
dpll_flag_override and dpll_flag_value parameters).
Loading new data into a holding register not associated with the
synthesizer frequency programming does not reset or change the
synthesizer. The synthesizer should not lose lock before, during,
or after a new serial word load that does not change the
programmed frequency.
VCO Auto-Tuning Loop
A VCO auto-tuning loop provides the proper 7-bit coarse tuning
setting for the VCO switch capacitors in the VCO output. This sets
the oscillation frequency as close to target as possible before
starting fine analog tuning.
When VCO auto-tuning is enabled, the PLL performs a seven-step
successive approximation process to digitally tune the VCO close
to the final programmed frequency. Once that is complete, analog
tuning is switched in to lock the VCO to the programmed
frequency.
The auto-tuning loop is designed to compensate process variation
so that the VCO fine tuning range can be reduced to cover
temperature variation only. It significantly reduces VCO gain (Kv)
which reduces VCO phase noise.
There are two conditions that enable the VCO auto-tuning
function: a Power-On-Reset (POR) and a change in frequency. The
difference in the program flow under each of these conditions is
illustrated in Figure 5. Under either condition, dpll_en (bit [20] of
Word 1) should first be cleared so that a rising edge pulse can be
generated. Following this pulse, set dpll_en to enable VCO auto-
tuning.
A POR timing diagram is shown in Figure 6. VCO auto-tuning
details in the frequency and time domains are shown in Figure 7.
DATA
t
DHD
t
DSU
CLK
t
CLE
t
LEC
t
LEW
LE
S1053
t
CKH
t
CKL
Figure 3. SKY73121-11 Serial Data Input Timing Diagram (MSB First)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
200888B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 1, 2009
3
DATA SHEET • SKY73121-11 VCO/SYNTHESIZER
Table 2. CLK, DATA, LE Preset Timing Parameters
Parameter
Input high voltage (V
IH
)
Input low voltage (V
IL
)
Input current (l
DIG
)
Clock frequency
Clock high (t
CKH
)
Clock low (t
CKL
)
Data set up (t
DSU
)
Data hold (t
DHD
)
Clock to latch enable (t
CLE
)
Latch enable width (t
LEW
)
Latch enable to clock (t
LEC
)
Word length
Number of words
Current drain
1.6 V
0.3 V
1 A (maximum)
15 MHz (maximum)
15 ns (minimum)
15 ns (minimum)
20 ns (minimum)
10 ns (minimum)
20 ns (minimum)
15 ns (minimum)
15 ns (minimum)
26 bits
4
2 A
Value
Power-On
Preset
CLK
DATA
(Words 0-3, bits [25:0])
Load
Register
Bits [25:2]
Operation
Mode
Register
Latch
Word 0
Bits [25:2]
Auto
Calibration
Control
Register
Latch
Word 1
Bits [25:2]
Frequency
Word 2
Bits [25:2]
Control 1
Register
Latch
Frequency
Control 2
Register
Latch
Word 3
Bits [25:2]
Words 0-3
Bits [1:0]
LE
2 LSB Decode
(Register Address,
Bits [1:0])
S918
Figure 4. Serial Bus Block Diagram
Table 3. SKY73121-11 Hold Registers and Addresses
Hold Register Name
Operation Mode
Auto Calibration Control
Frequency Control 1
Frequency Control 2
Hold Register Address (Binary) in Load Register Words
Bit [1]
0
0
1
1
Bit [0]
0
1
0
1
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
4
December 1, 2009 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200888B
DATA SHEET • SKY73121-11 VCO/SYNTHESIZER
Table 4. Load Register Word 0 (Programs the Operation Mode Register) (1 of 2)
Parameter
Function
State Description
Recommended
Operational Value
(Binary)
00
Bits [4:2]:
0 0 0 = 200
0 0 1 = 400
0 1 0 = 600
0 1 1 = 800
1 0 0 = 1000
1 0 1 = 1200
1 1 0 = 1400
1 1 1 = 1600
cp_delay
Charge pump delay [6:5]
Bits [6:5]:
0 0 = 2 nsec
0 1 = 4 nsec
1 0 = 7 nsec
1 1 = 9 nsec
NOTE: this device is fixed at 2 nsec.
pd_polar
Polarity of phase detector [7]
Bit [7]:
0 = Negative
1 = Positive
NOTE: this device is fixed at negative polarity.
cp_tristate
Tri-state selection for the transmit PLL
charge pump output [8]
Bit [8]:
0 = Charge pump in normal functional mode
1 = Charge pump disabled/tri-stated
Reserved
Bit [12] Bit [11] Bit [10]: N-Cntr/R1-Divider
ΣΔ
Mod
Voltage
Voltage
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
=
=
=
=
=
0V
1.8 V
1.8 V
2.4 V
2.4 V
0V
1.8 V
2.4 V
1.8 V
2.4 V
–
0
100
0
0
A
A
A
A
A
A
A
A
Application
dependent
wd_0, wd_1
cp_output
Address bits [1:0]. Must be set to 00b (see
Table 3)
Charge pump setting [4:2]
00
rsvd
sd_sel
Reserved [9]
Internal operating voltage control bit for
synthesizer [10]
Note: this bit needs to be programmed
together with bits [11] and [12].
nr_sel
Internal operating voltage control bit for N-
counter and R1 divider [11]
See sd_sel parameter (bit [10])
This bit needs to be programmed together with bits [10] and [12].
pll_en
Internal operating voltage control bit for PLL
[12]
See sd_sel parameter (bit [10])
This bit needs to be programmed together with bits [10] and [11].
–
ref_bw_sel
Reference buffer bandwidth [14:13]
Bits [14:13]:
0 0 = 20 MHz
0 1 = 30 MHz
1 0 = 40 MHz
1 1 = 50 MHz
11
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
200888B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • December 1, 2009
5
MicroPython开源版块
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
