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82C87H

March 1997

CMOS Octal Inverting Bus Transceiver

Description

The Intersil 82C87H is a high performance CMOS Octal

Transceiver manufactured using a self-aligned silicon gate

CMOS process (Scaled SAJI IV). The 82C87H provides a full

eight-bit bi-directional bus interface in a 20 pin package. The

Transmit (T) control determines the data direction. The active

low output enable (OE) permits simple interface to the

80C86, 80C88 and other microprocessors. The 82C87H has

gated inputs, eliminating the need for pull-up/pull-down resis-

tors and reducing overall system operating power dissipation.

The 82C87H provides inverted data at the outputs.

Features

• Full Eight Bit Bi-Directional Bus Interface

• Industry Standard 8287 Compatible Pinout

• High Drive Capability

- B Side I

OL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

- A Side I

OL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA

• Three-State Inverting Outputs

• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.

• Gated Inputs

- Reduce Operating Power

- Eliminate the Need for Pull-Up Resistors

• Single 5V Power Supply

• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA

• Operating Temperature Range

- C82C87H . . . . . . . . . . . . . . . . . . . . . . . . . 0

o

C to +70

o

C

- I82C87H . . . . . . . . . . . . . . . . . . . . . . . . -40

o

C to +85

o

C

- M82C87H . . . . . . . . . . . . . . . . . . . . . . -55

o

C to +125

o

C

Ordering Information

PART NUMBERS

5MHz

CP82C87H-5

IP82C87H-5

CS82C87H-5

IS82C87H-5

CD82C87H-5

ID82C87H-5

MD82C87H-5/B

5962-

8757702RA

MR82C87H-5/B

5962-

87577022A

8MHz

PACK-

AGE

TEMP.

RANGE

0

o

C to +70

o

C

PKG.

NO.

E20.3

CP82C87H 20 Ld

PDIP

IP82C87H

CS82C87H 20 Ld

PLCC

IS82C87H

CD82C87H 20 Ld

CERDIP

ID82C87H

-

SMD #

20 Pad

CLCC

SMD #

-40

o

C to +85

o

C E20.3

0

o

C to +70

o

C

N20.35

-40

o

C to +85

o

C N20.35

0

o

C to +70

o

C

F20.3

-40

o

C to +85

o

C F20.3

-55

o

C to

+125

o

C

F20.3

-55

o

C to

+125

o

C

J20.A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

|

Copyright

©

Intersil Corporation 1999

File Number

2978.1

4-325

82C87H

Pinouts

82C87H (PDIP, CERDIP)

TOP VIEW

82C87H (PLCC, CLCC)

TOP VIEW

V

CC

A2

A1

A0

B0

TRUTH TABLE

T

X

H

L

OE

H

L

A

Hi-Z

I

O

B

Hi-Z

O

I

A0 1

A1 2

A2 3

A3 4

A4 5

A5 6

A6 7

A7 8

OE 9

GND 10

20 V

CC

19 B0

18 B1

17 B2

16 B3

15 B4

14 B5

13 B6

12 B7

11 T

A6 7

A7 8

A3 4

A4 5

A5 6

3

2

1

20

19

18 B1

17 B2

16 B3

15 B4

14 B5

H

L

I

O

X

Hi-Z

= Logic One

= Logic Zero

= Input Mode

= Output Mode

= Don’t Care

= High Impedance

PIN NAMES

9

OE

10

GND

11

T

12

B7

13

B6

A

0

-A

7

B

0

-B

7

T

OE

DESCRIPTION

Local Bus Data I/O Pins

System Bus Data I/O Pins

Transmit Control Input

Active Low Output Enable

4-326

82C87H

Functional Diagram

A0

B0

Decoupling Capacitors

The transient current required to charge and discharge the

300pF load capacitance speciﬁed in the 82C86H/87H data

sheet is determined by:

I

=

C

L

(

dv

⁄

dt

)

(EQ. 4)

A1

A2

A3

A4

A5

A6

A7

B1

B2

B3

B4

B5

B6

B7

Assuming that all outputs change state at the same time and

that dv/dt is constant;

(

V CC

×

80%

)

-

I

=

C

L

------------------------------------

tR

⁄

tF

(EQ. 5)

where tR = 20ns, V

CC

= 5.0V, C

L

= 300pF on each eight out-

puts.

I

=

(

80

×

300

×

10

=

480mA

–

12

) × (

5.0V

×

0.8

) ⁄ (

20

×

10

–

9

)

(EQ. 6)

OE

T

Gated Inputs

During normal system operation of a latch, signals on the

bus at the device inputs will become high impedance or

make transitions unrelated to the operation of the latch.

These unrelated input transitions switch the input circuitry

and typically cause an increase in power dissipation in

CMOS devices by creating a low resistance path between

V

CC

and GND when the signal is at or near the input switch-

ing threshold. Additionally, if the driving signal becomes high

impedance (“ﬂoat” condition), it could create an indetermi-

nate logic state at the inputs and cause a disruption in

device operation.

The Intersil 82C8X series of bus drivers eliminates these

conditions by turning off data inputs when data is latched

(STB = logic zero for the 82C82/83H) and when the device is

disabled (OE = logic one for the 82C87H/87H). These gated

inputs disconnect the input circuitry from the V

CC

and

ground power supply pins by turning off the upper P-Chan-

nel and lower N-Channel (See Figures 1 and 2). No current

ﬂow from V

CC

to GND occurs during input transitions and

invalid logic states from ﬂoating inputs are not transmitted.

The next stage is held to a valid logic level internal to the

device.

D.C. input voltage levels can also cause an increase in ICC if

these input levels approach the minimum V

IH

or maximum

V

IL

conditions. This is due to the operation of the input cir-

cuitry in its linear operating region (partially conducting

state). The 82C8X series gated inputs mean that this condi-

tion will occur only during the time the device is in the trans-

parent mode (STB = logic one). ICC remains below the

maximum ICC standby speciﬁcation of 10µA during the time

inputs are disabled, thereby greatly reducing the average

power dissipation of the 82C8X series devices.

This current spike may cause a large negative voltage spike on

V

CC

which could cause improper operation of the device. To ﬁl-

ter out this noise, it is recommended that a 0.1µF ceramic disc

capacitor be placed between V

CC

and GND at each device,

with placement being as near to the device as possible.

V

CC

P

N

STB

DATA IN

N

P

INTERNAL

DATA

V

CC

N

FIGURE 3. 82C82/83H

V

CC

P

OE

P

DATA IN

V

CC

P

N

INTERNAL

DATA

FIGURE 4. 82C86H/87H GATED INPUTS

4-327

82C87H

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V

Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to V

CC

+0.5V

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Information

Thermal Resistance (Typical)

θ

JA

(

o

C/W)

θ

JC

(

o

C/W)

CERDIP Package . . . . . . . . . . . . . . . .

70

16

CLCC Package . . . . . . . . . . . . . . . . . .

80

20

PDIP Package . . . . . . . . . . . . . . . . . . .

75

N/A

PLCC Package . . . . . . . . . . . . . . . . . .

75

N/A

o

C to +150

o

C

Storage Temperature Range . . . . . . . . . . . . . . . . . . -65

Maximum Junction Temperature Hermetic Package . . . . . . . +175

o

C

Maximum Junction Temperature Plastic Package. . . . . . . . . +150

o

C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300

o

C

(PLCC - Lead Tips Only)

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range

C82C87H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0

o

C to +70

o

C

I82C87H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40

o

C to +85

o

C

M82C87H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55

o

C to +125

o

C

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

DC Electrical Speciﬁcations

V

CC

= 5.0V

±

10%; T

A

= 0

o

C to +70

o

C (C82C87H);

T

A

= -40

o

C to +85

o

C (I82C87H);

T

A

= -55

o

C to +125

o

C (M82C87H)

MIN

2.0

2.2

-

MAX

-

0.8

UNITS

V

TEST CONDITIONS

C82C87H, I82C87H

M82C87H (Note 1)

SYMBOL

V

IH

PARAMETER

Logical One

Input Voltage

V

IL

V

OH

Logical Zero Input Voltage

Logical One Output Voltage

B Outputs

A Outputs

A or B Outputs

3.0

V

CC

-0.4

-

V

I

OH

= -8mA

I

OH

= -4mA

I

OH

= -100µA

V

OL

Logical Zero Output Voltage

B Outputs

A Outputs

-

-10.0

-

0.45

10.0

10

1

V

µA

mA/MHz

I

OL

= 20mA

I

OL

= 12mA

V

IN

= GND or V

CC

DIP Pins 9, 11

VO = GND or V

CC

, OE

≥

V

CC

-0.5V

DIP Pins 1 - 8, 12 - 19

V

IN

= V

CC

or GND, V

CC

= 5.5V, Outputs Open

T

A

= +25

o

C, Typical (See Note 2)

I

IO

ICCSB

ICCOP

NOTES:

Input Leakage Current

Output Leakage Current

Standby Power Supply

Current

Operating Power Supply

Current

1. V

IH

is measured by applying a pulse of magnitude = V

IH(MIN)

to one data input at a time and checking the corresponding device output for

a valid logical “1” during valid input high time. Control pins (T, OE) are tested separately with all device data input pins at V

CC

-0.4.

2. Typical ICCOP = 1mA/MHz of read/ cycle time. (Example: 1.0µs read/write cycle time = 1mA).

Capacitance

SYMBOL

CIN

T

A

= +25

o

C

PARAMETER

Input Capacitance

B Inputs

A Inputs

18

14

pF

Freq = 1MHz, all measurements are

referenced to device GND

TYPICAL

UNITS

TEST CONDITIONS

4-328

82C87H

AC Electrical Speciﬁcations

V

CC

= 5.0V

±

10%;

Freq = 1MHz

T

A

= 0

o

C to +70

o

C (C82C87H);

T

A

= -40

o

C to +85

o

C (I82C87H);

T

A

= -55

o

C to +125

o

C (M82C87H)

NOTE 4

82C87H

MAX

82C87H-5

MAX

SYMBOL

(1)

TIVOV

PARAMETER

Input to Output Delay

Inverting

Non-Inverting

MIN

UNITS

TEST CONDITIONS

Notes 1, 2

5

10

5

10

-

30

32

-

30

50

20

35

-

35

65

20

ns

Notes 1, 2

Note 3

(2)

(3)

(4)

(5)

(6)

(7)

TEHTV

TTVEL

TEHOZ

TELOV

TR, TF

TEHEL

Transmit/Receive Hold Time

Transmit/Receive Setup Time

Output Disable Time

Output Enable Time

Input Rise/Fall Times

Minimum Output Enable High Time

82C87H

82C87H-5

30

35

-

ns

NOTES:

1. All AC parameters tested as per test circuits and deﬁnitions in timing waveforms and test load circuits. Input rise and fall times are driven

at 1ns/V.

2. Input test signals must switch between V

IL

- 0.4V and V

IH

+0.4V.

3. A system limitation only when changing direction. Not a measured parameter.

4. 82C87H is available in commercial and industrial temperature ranges only. 82C87H-5 is available in commercial, industrial and military

temperature ranges.

Timing Waveform

TR, TF (6)

INPUTS

2.0V

0.8V

TEHEL (7)

OE

(1)

TIVOV

OUTPUTS

(4)

TEHOZ

V

OH

-0.1V

V

OL

+0.1V

TEHTV (2)

T

TELOV (5)

3.0V

0.45V

TTVEL (3)

4-329

82C87H

82C87H概述

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