SN54/74LS195A
UNIVERSAL 4-BIT
SHIFT REGISTER
The SN54 / 74LS195A is a high speed 4-Bit Shift Register offering typical
shift frequencies of 39 MHz. It is useful for a wide variety of register and
counting applications. It utilizes the Schottky diode clamped process to
achieve high speeds and is fully compatible with all Motorola TTL products.
UNIVERSAL 4-BIT
SHIFT REGISTER
LOW POWER SCHOTTKY
•
•
•
•
•
Typical Shift Right Frequency of 39 MHz
Asynchronous Master Reset
J, K Inputs to First Stage
Fully Synchronous Serial or Parallel Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
VCC
16
Q0
15
Q1
14
Q2
13
Q3
12
Q3
11
CP
10
PE
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
J SUFFIX
CERAMIC
CASE 620-09
16
1
16
1
N SUFFIX
PLASTIC
CASE 648-08
1
MR
2
J
3
K
4
P0
5
P1
6
P2
7
P3
8
GND
16
PIN NAMES
LOADING
(Note a)
HIGH
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
1
D SUFFIX
SOIC
CASE 751B-03
PE
P0 – P3
J
K
CP
MR
Q0 – Q3
Q3
Parallel Enable (Active LOW) Input
Parallel Data Inputs
First Stage J (Active HIGH) Input
First Stage K (Active LOW) Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs (Note b)
Complementary Last Stage Output (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
9
4
5
6
7
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.
Temperature Ranges.
2
10
3
J
CP
K
PE P0 P1 P2 P3
Q3
11
MR Q0 Q1 Q2 Q3
1 15 14 13 12
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-366
SN54/74LS195A
LOGIC DIAGRAM
PE
9
2
J
3
K
4
P0
5
P1
6
P2
7
P3
1
MR
10
CP
R CD Q0
CP
S
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
Q0
15
R CD
CP
S
Q0
14
R CD
CP
S
Q2
13
R CD Q3
CP
S
Q3
12
11
Q0
Q1
Q2
Q3 Q3
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the functional
characteristics of the LS195A 4-Bit Shift Register. The device
is useful in a wide variety of shifting, counting and storage
applications. It performs serial, parallel, serial to parallel, or
parallel to serial data transfers at very high speeds.
The LS195A has two primary modes of operation, shift right
(Q0 Q1) and parallel load which are controlled by the state of
the Parallel Enable (PE) input. When the PE input is HIGH,
serial data enters the first flip-flop Q0 via the J and K inputs and
is shifted one bit in the direction Q0 Q1 Q2 Q3 following
each LOW to HIGH clock transition. The JK inputs provide the
flexibility of the JK type input for special applications, and the
simple D type input for general applications by tying the two
pins together. When the PE input is LOW, the LS195A appears
as four common clocked D flip-flops. The data on the parallel
inputs P0, P1, P2, P3 is transferred to the respective Q0, Q1,
Q2, Q 3 outputs following the LOW to HIGH clock transition.
Shift left operations (Q3 Q2) can be achieved by tying the Qn
Outputs to the Pn–1 inputs and holding the PE input LOW.
All serial and parallel data transfers are synchronous,
occurring after each LOW to HIGH clock transition. Since the
LS195A utilizes edge-triggering, there is no restriction on the
activity of the J, K, Pn and PE inputs for logic operation —
except for the set-up and release time requirements.
A LOW on the asynchronous Master Reset (MR) input sets
all Q outputs LOW, independent of any other input condition.
MODE SELECT — TRUTH TABLE
OPERATING MODES
Asynchronous Reset
Shift, Set First Stage
Shift, Reset First
Shift, Toggle First Stage
Shift, Retain First Stage
Parallel Load
INPUTS
MR
L
H
H
H
H
H
PE
X
h
h
h
h
I
J
X
h
I
h
I
X
K
X
h
I
I
h
X
Pn
X
X
X
X
X
pn
Q0
L
H
L
q0
q0
p0
Q1
L
q0
q0
q0
q0
p1
OUTPUTS
Q2
L
q1
q1
q1
q1
p2
Q3
L
q2
q2
q2
q2
p3
Q3
H
q2
q2
q2
q2
p3
L = LOW voltage levels
H = HIGH voltage levels
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition.
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition.
pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to
HIGH clock transition.
FAST AND LS TTL DATA
5-367
SN54/74LS195A
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
– 20
– 0.4
– 100
21
0.35
0.5
20
IIH
IIL
IOS
ICC
V
µA
mA
mA
mA
mA
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C)
Limits
Symbol
fMAX
tPLH
tPHL
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay,
Clock to Output
Propagation Delay,
MR to Output
Min
30
Typ
39
14
17
19
22
26
30
Max
Unit
MHz
ns
ns
VCC = 5.0 V
CL = 15 pF
Test Conditions
AC SETUP REQUIREMENTS
(TA = 25°C)
Limits
Symbol
tW
tW
ts
ts
trec
trel
th
Parameter
CP Clock Pulse Width
MR Pulse Width
PE Setup Time
Data Setup Time
Recovery Time
PE Release Time
Data Hold Time
0
Min
16
12
25
15
25
10
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
VCC = 5.0 V
Test Conditions
FAST AND LS TTL DATA
5-368
SN54/74LS195A
DEFINITIONS OF TERMS
SETUP TIME(ts) —is defined as the minimum time required
for the correct logic level to be present at the logic input prior
to the clock transition from LOW to HIGH in order to be
recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
tW
CLOCK
OUTPUT
tPHL
1.3 V
CONDITIONS: J = PE = MR = H
K=L
1.3 V
1.3 V
tPLH
1.3 V
PE
J&K
P0 P1 P2 P3
th(L) = 0
CLOCK
OUTPUT*
1.3 V
ts(H)
th(H) = 0
ts(L)
th(L) = 0
ts(L)
ts(H)
th(H) = 0
1.3 V
1.3 V
Figure 1. Clock to Output Delays and
Clock Pulse Width
CONDITIONS: MR = H
*J AND K SET-UP TIME AFFECTS Q0 ONLY
tW
1.3 V
MR
Figure 3. Setup (ts) and Hold (th) Time for Serial Data
(J & K) and Parallel Data (P0, P1, P2, P3)
1.3 V
trec
CLOCK
tPHL
OUTPUT
1.3 V
1.3 V
LOAD PARALLEL DATA
PE
ts(L)
CLOCK
1.3 V
trel
1.3 V
ts(H)
LOAD SERIAL DATA
SHIFT RIGHT
1.3 V
trel
1.3 V
CONDITIONS: PE = L
PO = P1 = P2 = P3 = H
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
OUTPUT
Qn = Pn
Qn* = Qn-1
CONDITIONS: MR = H
*Q0 STATE WILL BE DETERMINED BY J AND K INPUTS .
Figure 4. Setup (ts) and Hold (th) Time for PE Input
FAST AND LS TTL DATA
5-369
-A-
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
3.
CONTROLLING DIMENSION: MILLIMETER.
DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4.
MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5.
751B 01 IS OBSOLETE, NEW STANDARD
751B 03.
16
9
-B-
1
8
P
8 PL
0.25 (0.010)
M
B
M
R X 45°
G
-T-
D
16 PL
0.25 (0.010)
M
C
SEATING
PLANE
K
T
B
S
M
F
J
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
3.80
1.35
0.35
0.40
10.00
4.00
1.75
0.49
1.25
INCHES
MIN
MAX
0.386
0.150
0.054
0.014
0.016
0.393
0.157
0.068
0.019
0.049
1.27 BSC
0.19
0.10
0
0.25
0.25
7
0.050 BSC
0.008
0.004
0
0.009
0.009
7
°
°
°
°
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
Case 648-08 N Suffix
16-Pin Plastic
-A-
16
9
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
3.
CONTROLLING DIMENSION: INCH.
DIMENSION L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4.
DIMENSION B" DOES NOT INCLUDE MOLD
FLASH.
5.
6.
ROUNDED CORNERS OPTIONAL.
648 01 THRU 07 OBSOLETE, NEW STANDARD
648 08.
B
1
8
F
S
C
-T-
K
SEATING
PLANE
L
H
G
D
16 PL
0.25 (0.010)
M
J
M
T
A
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
MILLIMETERS
MIN
MAX
18.80
6.35
3.69
0.39
1.02
19.55
6.85
4.44
0.53
1.77
INCHES
MIN
MAX
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.070
2.54 BSC
1.27 BSC
0.21
2.80
7.50
0
0.38
3.30
7.74
10
0.100 BSC
0.050 BSC
0.008
0.110
0.295
0
0.015
0.130
0.305
10
°
°
°
°
0.51
1.01
0.020
0.040
-A-
16
9
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
-B-
1
8
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
C
L
5. 620 01 THRU 08 OBSOLETE, NEW STANDARD
620 09.
-T-
SEATING
PLANE
K
E
F
D
16 PL
0.25 (0.010)
M
N
G
T
A
S
M
J
16 PL
0.25 (0.010)
M
T
B
S
DIM
A
B
C
D
E
F
G
J
K
L
M
N
MILLIMETERS
MIN
MAX
19.05
6.10
19.55
7.36
4.19
0.39
0.53
INCHES
MIN
MAX
0.750
0.240
0.770
0.290
0.165
0.015
0.021
1.27 BSC
1.40
1.77
0.050 BSC
0.055
0.070
2.54 BSC
0.23
0.27
5.08
7.62 BSC
0
0.100 BSC
0.009
0.011
0.200
0.300 BSC
0
°
15
°
°
15
°
0.39
0.88
0.015
0.035
FAST AND LS TTL DATA
5-370
嵌入式系统
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