82562EZ(EX)/82547GI(EI) Dual
Footprint
Design Guide
Networking Silicon
317520-002
Revision 2.2
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82562EZ(EX)/82547GI(EI) Dual Footprint
Revision History
Revision
0.25
0.75
Revision Date
Jul 2002
Sep 2002
Description
Initial publication of preliminary design guide information.
Published revised design guide information:
• Added information on EEPROM settings
• Added design checklist
• Revised reference design schematic
• Revised Ball Number to signal mapping Table to conform to changes in
82547EI datasheet rev 0.75
1.0
Oct 2002
Published revised design guide information:
• Added layout checklist
• Updated LAN disable circuit
• Removed EEPROM information due to publication of separate guides
1.5
Sep 2003
Published revised design guide information:
• Added 82547GI coverage
• Removed Confidential status
• Updated schematics, removed redundant caps
• Revised LAN disable circuit
1.6
Nov 2004
Added crystal start-up information. Information includes:
• New crystal parameters
• Crystal selection guidelines
• Crystal validation methods
• Crystal testing methods
Changed signal name FL_SO to the correct signal name FLSH_SO.
Added 82562EX applicability.
Added new values for TX and RX terminations (next to LAN silicon). New
values are now 110
Ω
for both TX and RX terminations.
Added new starting values for RBIAS100 and RBIAS10. New starting values
are now 649
Ω
for RBIAS100 and 619
Ω
for RBIAS10.
Updated reference schematics to reflect new Tx and Rx termination values,
new LAN disable circuit, and RBIAS100/RBIAS10 values.
Removed excess capacitors and changed pins F12 and H12 to no connects.
Added a 1K
Ω
resistor to pin A13 output.
1.7
Jan 2005
• Changed text in the Catalyst EEPROM revision H table note from
“Revision H or higher not supported” to “Revision H is not supported”.
• Removed the Design and Layout Checklists. These checklists are now
separate Microsoft* Excel spreadsheets.
1.8
Jan 2005
Updated reference schematics to reflect current differential pair termination
resistor values for the 82547GI/EI.
Updated section 4.2.1 “Termination Resistors for Designs Based on 82562EZ/
EX PLC Device” to reflect current resistor and RBIAS values.
Updated section 4.3.1 “Termination Resistors for Designs Based on 8257GI(EI)
Gigabit Ethernet Controller” to reflect current resistor values.
1.9
2.0
2.1
2.2
June 2006
Feb 2007
June 2007
Jan 2008
Updated reference schematics for signals EE_MODE and JTAG_TRST#
(changed resistor values from 1 K
Ω
to 100
Ω).
Updated sections 3.1.3, 3.1.1.8, and Table 5 in section 3.1.1 (changed max
ESR rate from 20
Ω
to 10
Ω
for the 82547GI/EI).
Updated reference schematics: sheets 4 and 6.
Added Table 6; approved crystals for the 82547GI(EI).
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82562EZ(EX)/82547GI(EI) Dual Footprint
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82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
Contents
1.0
1.1
1.2
1.3
2.0
2.1
2.2
Introduction......................................................................................................................... 1
Scope............................................................................................................................................ 1
Reference Documents .................................................................................................................. 2
Product Codes .............................................................................................................................. 2
System Data Port Interfaces .............................................................................................. 3
LCI Connection to 82562EZ(EX) Platform LAN Connect Device ................................................. 3
CSA Port Connection to 82547GI(EI) Gigabit Ethernet Controller ............................................... 4
2.2.1 Generation/Distribution of Reference Voltages ............................................................... 4
2.2.2 CSA Port Resistive Compensation .................................................................................. 5
Ethernet Component Design Guidelines ............................................................................ 7
General Design Considerations for Ethernet Controllers.............................................................. 7
3.1.1 Crystal Selection Parameters .......................................................................................... 7
3.1.2 Reference Crystal ..........................................................................................................10
3.1.3 Reference Crystal Selection ..........................................................................................11
3.1.4 Circuit Board ..................................................................................................................11
3.1.5 Temperature Changes...................................................................................................11
3.1.6 Integrated Magnetics Module ........................................................................................12
Designing with the 82562EZ(EX) Platform LAN Connect Device...............................................12
3.2.1 82562EZ/EX PLC Device LAN Disable Guidelines .......................................................12
3.2.2 Serial EEPROM for 82562EZ(EX) Implementations......................................................13
3.2.3 Magnetics Modules for 82562EZ(EX) PLC Device........................................................14
3.2.4 Power Supplies for 82562EZ(EX) PLC Implementations ..............................................14
3.2.5 82562EZ(EX) Device Test Capability ............................................................................14
Designing with the 82547GI(EI) Gigabit Ethernet Controller ......................................................14
3.3.1 82547GI(EI) Ethernet Controller LAN Disable Guidelines .............................................14
3.3.2 Serial EEPROM for 82547GI(EI) Controller Implementations .......................................15
3.3.3 EEPROM Map Information ............................................................................................17
3.3.4 Magnetics Modules for 82547GI(EI) Controller Applications .........................................17
3.3.5 Power Supplies for the 82547GI(EI) Device ..................................................................17
3.3.6 82547GI(EI) Controller Power Supply Filtering..............................................................18
3.3.7 82547GI(EI) Controller Power Management and Wake Up...........................................18
3.3.8 82547GI(EI) Device Test Capability ..............................................................................19
Ethernet Component Layout Guidelines ..........................................................................21
General Layout Considerations for Ethernet Controllers ............................................................21
4.1.1 Guidelines for Component Placement ...........................................................................21
4.1.2 Crystals..........................................................................................................................22
4.1.3 Board Stack Up Recommendations...............................................................................22
4.1.4 Differential Pair Trace Routing.......................................................................................23
4.1.5 Signal Trace Geometry..................................................................................................24
4.1.6 Trace Length and Symmetry .........................................................................................24
4.1.7 Impedance Discontinuities.............................................................................................25
4.1.8 Reducing Circuit Inductance..........................................................................................25
4.1.9 Signal Isolation ..............................................................................................................25
4.1.10 Power and Ground Planes.............................................................................................25
3.0
3.1
3.2
3.3
4.0
4.1
v
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