Philips Semiconductors
Product specification
Octal bus transceiver/register (3-State)
74LVC646A
FEATURES
•
Wide supply voltage range of 1.2V to 3.6V
•
Flow-through pin-out architecture
•
In accordance with JEDEC standard no. 8-1A
•
CMOS low power consumption
•
Direct interface with TTL levels
•
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC646A is a high performance, low-power, low-voltage
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC646A consist of non-inverting bus transceiver circuits
with 3-State outputs, D-type flip-flops and control circuitry arranged
for multiplexed transmission of data directly from the internal
registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal
registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH
logic level. Output enable (OE) and direction (DIR) inputs are
provided to control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in either the
‘A’ or ‘B’ register, or in both. The select source inputs (SAB and
SBA) can multiplex stored and real-time (transparent mode) data.
The direction (DIR) input determines which bus will receive data
when OE is active (LOW). In the isolation mode (OE = HIGH), ‘A’
data may be stored in the ‘B’ register and/or ‘B’ data may be stored
in the ‘A’ register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, ‘A’ or ‘B’ may be driven at a time.
The ‘646A’ is functionally identical to the ‘648A’ but has non-inverting
data paths.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
≤
2.5 ns
PARAMETER
SYMBOL
t
PHL
/t
PLH
f
max
C
I
C
I/O
C
PD
Propagation delay
An to Yn
Maximum clock frequency
Input capacitance
Input/output capacitance
Power dissipation capacitance per gate
Notes 1, 2
CONDITIONS
C
L
= 50pF
V
CC
= 3.3V
TYPICAL
3.9
250
5.0
10
26
UNIT
ns
MHz
pF
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
V
CC2
x f
i
)Σ
(C
L
V
CC2
f
o
) where:
P
D
= C
PD
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
Σ
(C
L
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
24-Pin Plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH
AMERICA
74LVC646A D
74LVC646A DB
74LVC646A PW
NORTH AMERICA
74LVC646A D
74LVC646A DB
7LVC646APW DH
PKG. DWG. #
SOT137-1
SOT340-1
SOT355-1
1998 Jul 29
2
853-2105 19803
Philips Semiconductors
Product specification
Octal bus transceiver/register (3-State)
74LVC646A
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
1
SYMBOL
CP
AB
S
AB
DIR
A
0
to A
7
GND
B
0
to B
7
OE
S
BA
CP
BA
V
CC
FUNCTION
‘A’ to ‘B’ clock input
(LOW-to-HIGH, edge-triggered)
Select ‘A’ to ‘B’ source input
Direction control input
‘A’ data inputs/outputs
Ground (0V)
‘B’ data inputs/outputs
Output enable input (active LOW)
Select ‘B’ to ‘A’ source input
‘B’ to ‘A’ clock input
(LOW-to-HIGH, edge-triggered)
Positive supply voltage
CP AB
S AB
DIR
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
V CC
CP BA
S BA
OE
B0
B1
B2
B3
B4
B5
B6
B7
2
3
4, 5, 6, 7, 8,
9, 10, 11
12
20, 19, 18, 17,
16, 15, 14, 13
21
22
23
24
A 6 10
A7
GND
11
12
SV00766
FUNCTION TABLE
INPUTS
OE
X
X
H
H
L
L
L
L
*
DIR
X
X
X
X
L
L
H
H
CP
AB
↑
X
↑
H or L
X
X
X
H or L
CP
BA
X
↑
↑
H or L
X
H or L
X
X
S
AB
X
X
X
X
X
X
L
H
S
BA
X
X
X
X
L
H
X
X
DATA I/O *
A
0
to A
7
input
un *
input
output
input
B
0
to B
7
un *
input
input
input
output
store A, B unspecified *
store B, A unspecified *
store A and B data,
isolation hold storage
real-time B data to A bus
stored B data to A bus
real-time A data to B bus
stored A data to B bus
FUNCTION
The data output functions may be enabled or disabled by
various signals at the OE and DIR inputs. Data input
functions are always enabled, i.e., data at the bus inputs will
be stored on every LOW-to-HIGH transition on the clock
inputs.
un
= unspecified
H
= HIGH voltage level
L
= LOW voltage level
X
= Don’t care
↑
= LOW-to-HIGH level transition
1998 Jul 29
3
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