TSC80251G1D
Extended 8–bit Microcontroller with Serial Communication
Interfaces
1. Description
The TSC80251G1D products are derivatives of the
T
EMIC
Microcontroller family based on the extended
8–bit C251 Architecture. This family of products is
tailored to 8–bit microcontroller applications requiring
an increased instruction throughput, a reduced operating
frequency or a larger addressable memory space. The
architecture can provide a significant code size
reduction when compiling C programs while fully
preserving the legacy of C51 assembly routines.
The TSC80251G1D derivatives are pin–out and
software compatible with standard 80C51/Fx/Rx with
extended on–chip data memory (1 Kbyte RAM) and up
to 256 Kbytes of external code and data. Additionally,
the TSC83251G1D provides on–chip code memory
(16 Kbytes ROM).
They provide transparent enhancements to Intel’s
8xC251Sx family with an additional Synchronous Serial
Link Controller (SSLC supporting I
2
C,
µWire
and SPI
protocols), a Keyboard interrupt interface and Power
Monitoring and Management features.
TSC80251G1D Mask ROM and ROMless derivatives
are optimized both for speed and for low power
consumption on a wide voltage range.
Notes:
This Datasheet provides the technical description of the TSC80251G1D derivatives. For further information on the device usage, please request
the TSC80251 Programmers’ Guide and the TSC80251G1D Design Guide.
For information on the EPROM/OTP devices, please refer to the TSC87251G1A Datasheet.
2. Typical Applications
D
ISDN terminals
D
High–Speed modems
D
PABX (SOHO)
D
Networking
D
Line cards
D
Computer peripherals
D
Printers
D
Plotters
D
Scanners
D
Banking machines
D
Barcode readers
D
Smart cards readers
D
High–end digital monitors
D
High–end joysticks
Purchase of TEMIC I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these components
in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
Rev. C
–
October 14, 1998
1
TSC80251G1D
3. Features
D
Pin–Out and software compatibility with standard
80C51 products and 80C51FA/FB/RA/RB
D
Plug–in replacement of Intel’s 80C251Sx
D
C251 core:
G
G
G
G
G
Intel’s MCS
R
251
step D compliance
83 ns Instruction cycle time @ 24 MHz
40–byte Register File
Registers Accessible as Bytes, Words or Dwords
Six–stage Instruction Pipeline
16–bit Internal Code Fetch
D
Secure 14–bit Hardware Watchdog Timer
D
Power Monitoring and Management
G
Power–Fail reset
G
Power–On reset (integrated on the chip)
G
Power–Off flag (cold and warm resets)
G
Software programmable system clock
G
Idle and Power–Down modes
D
Keyboard interrupt interface on Port 1
D
Non Maskable Interrupt input (NMI)
D
Real–time Wait states inputs (WAIT#/AWAIT#)
D
On–chip Code Verify with Encryption for Mask
ROM versions
D
ONCE mode and full speed Real–Time In–Circuit
Emulation support (Third Party Vendors)
D
High speed versions:
G
16 MHz and 24 MHz
G
5 V
±10
%
G
Typical operating current: 34 mA @ 24 MHz
23 mA @ 16 MHz
G
Power–Down mode typical current
≤
2
µA
D
Low voltage version:
G
2.7 V to 5.5 V
G
12 MHz operation
G
Typical operating current: 8 mA @ 3 V
G
Power–Down mode typical current
≤
1
µA
D
Temperature ranges:
G
Commercial (0°C to +70°C)
G
Industrial (–40°C to +85°C)
G
Option: extended range (–55°C to +125°C)
D
Packages:
G
PDIL 40, PLCC 44 and VQFP 44
G
Options: known good dice and ceramic packages
D
Enriched C51 Instruction Set
G
16–bit and 32–bit ALU
G
Compare and Conditional Jump Instructions
G
Expanded Set of Move Instructions
D
Linear Addressing
D
1 Kbyte of on–chip RAM
D
External memory space (Code/Data) programmable
from 64 Kbytes to 256 Kbytes
D
TSC83251G1D: 16 Kbytes of on–chip masked ROM
(Engineering
and
fast
production
with
TSC87251G1A OTP/EPROM version)
D
TSC80251G1D: ROMless version
D
Four 8–bit parallel I/O Ports (Ports 0, 1, 2 and 3 of the
standard 80C51)
D
Serial I/O Port: full duplex UART (80C51
compatible) with independent Baud Rate Generator
D
SSLC: Synchronous Serial Link Controller
G
I
2
C multi–master and slave protocols
G
µWire
and SPI master and slave protocols
D
Three 16–bit Timers/Counters (Timers 0, 1 and 2 of
the standard 80C51)
D
EWC: Event and Waveform Controller
G
Compatible with Intel’s Programmable Counter
Array (PCA)
G
Common 16–bit Timer/Counter reference with
four possible clock sources (Fosc/4, Fosc/12,
Timer 1 and external input)
G
Five modules with four programmable modes:
– 16–bit software Timer/Counter
– 16–bit Timer/Counter Capture Input and
software pulse measurement
– High–speed output and 16–bit software Pulse
Width Modulation (PWM)
– 8–bit hardware PWM without overhead
G
16–bit Watchdog Timer/Counter capability
2
Rev. C
–
October 14, 1998
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