74F51 Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert Gate
April 1988
Revised July 1999
74F51
Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert Gate
General Description
This device contains two independent logic units, one per-
forming a 2-2 AND-OR-INVERT and the other performing a
3-3 AND-OR-INVERT function.
Ordering Code:
Order Number
74F51SC
74F51SJ
74F51PC
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input I
IH
/I
IL
20
µA/−0.6
mA
−1
mA/20 mA
HIGH/LOW Output I
OH
/I
OL
1.0/1.0
50/33.3
A
n
, B
n
, C
n
, D
n
, E
n
, F
n
Inputs
O
n
Outputs
Function Table for 3-Input Gates
Inputs
A
0
H
X
B
0
H
X
C
0
H
X
D
0
X
H
E
0
X
H
F
0
X
H
Output
O
0
L
L
H
L
=
LOW Voltage Level
Function Table for 2-Input Gates
Inputs
A
1
H
X
B
1
H
X
C
1
X
H
D
1
X
H
Output
O
1
L
L
H
All other combinations
H
=
HIGH Voltage Level
All other combinations
X
=
Immaterial
© 1999 Fairchild Semiconductor Corporation
DS009468
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74F51
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−0.5V
to V
CC
−0.5V
to
+5.5V
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to
+70°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CCH
I
CCL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
Power Supply Current
−60
1.9
5.3
4.75
3.75
−0.6
−150
3.0
8.5
5.0
7.0
50
µA
µA
µA
V
µA
mA
mA
mA
mA
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All other pins grounded
V
IOD
=
150 mV
All other pins grounded
V
IN
=
0.5V
V
OUT
=
0V
V
O
=
HIGH
V
O
=
LOW
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
V
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
Min
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
Propagation Delay
A
n
, B
n
, C
n
, D
n
, E
n
, F
n
to O
n
2.0
1.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
3.7
2.6
Max
6.0
4.0
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
1.5
1.0
Max
6.5
4.5
ns
Units
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2
74F51
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
3
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74F51 Dual 2-Wide 2-Input; 2-Wide 3-Input AND-OR-Invert Gate
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
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2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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