3-STATE HEX BUFFERS
These devices are high speed hex buffers with 3-state outputs. They are
organized as single 6-bit or 2-bit / 4-bit, with inverting or non-inverting data (D)
paths. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power
Schottky loads when the Enable (E) is LOW.
When the Output Enable (E) is HIGH, the outputs are forced to a high
impedance “off” state. If the outputs of the 3-state devices are tied together,
all but one device must be in the high impedance state to avoid high currents
that would exceed the maximum ratings. Designers should ensure that Output
Enable signals to 3-state devices whose outputs are tied together are
designed so there is no overlap.
SN54/74LS365A
SN54/74LS366A
SN54/74LS367A
SN54/74LS368A
3-STATE HEX BUFFERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
16
1
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54
74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 1.0
– 2.6
12
24
Unit
V
°C
mA
mA
FAST AND LS TTL DATA
5-1
SN54/74LS365A
•
SN54/74LS366A
SN54/74LS367A
•
SN54/74LS368A
SN54 / 74LS365A
HEX 3-STATE BUFFER WITH
COMMON 2-INPUT NOR ENABLE
VCC
16
E2
15
14
13
12
11
10
9
SN54 / 74LS366A
HEX 3-STATE INVERTER BUFFER
WITH COMMON 2-INPUT NOR ENABLE
VCC
16
E2
15
14
13
12
11
10
9
1
E1
2
3
4
5
6
7
8
GND
1
E1
2
3
4
5
6
7
8
GND
TRUTH TABLE
INPUTS
E1
L
L
H
X
E2
L
L
X
H
D
L
H
X
X
L
H
(Z)
(Z)
OUTPUT
L
L
H
X
TRUTH TABLE
INPUTS
E1
E2
L
L
X
H
D
L
H
X
X
H
L
(Z)
(Z)
OUTPUT
SN54 / 74LS367A
HEX 3-STATE BUFFER
SEPARATE 2-BIT AND 4-BIT SECTIONS
VCC
16
E
15
14
13
12
11
10
9
SN54 / 74LS368A
HEX 3-STATE INVERTER BUFFER
SEPARATE 2-BIT AND 4-BIT SECTIONS
VCC
16
E
15
14
13
12
11
10
9
1
E
2
3
4
5
6
7
8
GND
1
E
2
3
4
5
6
7
8
GND
TRUTH TABLE
INPUTS
E
L
L
H
D
L
H
X
L
H
(Z)
OUTPUT
TRUTH TABLE
INPUTS
E
L
L
H
D
L
H
X
H
L
(Z)
OUTPUT
FAST AND LS TTL DATA
5-2
SN54/74LS365A
•
SN54/74LS366A
SN54/74LS367A
•
SN54/74LS368A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
S b l
VIH
VIL
VIK
VOH
Parameter
P
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
IOZH
IOZL
IIH
Output LOW Voltage
74
Output Off Current HIGH
Output Off Current LOW
Input HIGH Current
0.1
Input LOW Current
E Inputs
IIL
D Inputs
– 0.4
– 20
– 0.4
IOS
ICC
Short Circuit Current (Note 1)
Power Supply Current
LS365A, 367A
LS366A, 368A
– 40
– 225
24
21
0.35
0.5
20
– 20
20
V
µA
µA
µA
mA
mA
µA
mA
mA
2.4
3.1
0.25
0.4
V
V
2.4
– 0.65
3.4
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
U i
V
Test C di i
T
Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
p
g
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
,
,
or VIL per Truth Table
IOL = 12 mA
IOL = 24 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VOUT = 2.7 V
VCC = MAX, VOUT = 0.4 V
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX, VIN = 0.5 V
Either E Input at 2.0 V
VCC = MAX, VIN = 0.4 V
Both E Inputs at 0.4 V
VCC = MAX
VCC = MAX
mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
LS365A / LS367A
Symbol
S b l
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Parameter
P
Propagation Delay
Output Enable Time
Output Disable Time
Min
Typ
10
9.0
19
24
Max
16
22
35
40
30
35
LS366A / LS368A
Min
Typ
7.0
12
18
28
Max
15
18
35
45
32
35
Unit
U i
ns
ns
ns
Test C di i
T
Conditions
CL = 45 p ,
pF,
RL = 667
Ω
CL = 5.0 pF
FAST AND LS TTL DATA
5-3
FPGA/CPLD
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