INTEGRATED CIRCUITS
74F164
8-bit serial-in parallel-out shift register
Product specification
IC15 Data Handbook
1995 Sep 22
Philips
Semiconductors
Philips Semiconductors
Product specification
8-bit serial-in parallel-out shift register
74F164
FEATURES
•
Gated serial data inputs
•
Typical shift frequency of 100MHz
•
Asynchronous Master Reset
•
Buffered clock and data inputs
•
Fully synchronous data transfer
•
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F164 is an 8-bit edge-triggered shift register with serial data
entry and an output from each of the eight stages. Data is entered
through one of two inputs (Dsa, Dsb); either input can be used as an
active High enable for data entry through the other input. Both inputs
must be connected together or an unused input must be tied High.
Data shifts one place to the right on each Low-to-High transition of
the clock (CP) input, and enters into Q0 the logical AND of the two
data inputs (Dsa, Dsb) that existed one setup time before the rising
edge. A Low level on the Master Reset (MR) input overrides all
other inputs and clears the register asynchronously, forcing all
outputs Low.
PIN CONFIGURATION
Dsa
Dsb
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
14 V
CC
13 Q7
12 Q6
11 Q5
10 Q4
9
8
MR
CP
SF00717
TYPE
74F164
TYPICAL f
max
100MHz
TYPICAL SUPPLY
CURRENT (TOTAL)
33mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
14-pin plastic DIP
14-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
74F164N
74F164D
INDUSTRIAL RANGE
V
CC
= 5V
±10%,
T
amb
= –40°C to +85°C
I74F164N
I74F164D
DRAWING
NUMBER
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
Dsa, Dsb
CP
MR
Q0 – Q7
Data inputs
Clock pulse input (active rising edge)
Master reset input (active-Low)
Data outputs
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
SRG8
8
9
1
2
1
R
&
C1/→
8
9
CP
MR
Dsa
Dsb
2
1D
3
4
5
6
10
Q0 Q1 Q3 Q4 Q0 Q1 Q3 Q4
3
4
5
6 10 11
12 13
11
12
13
V
CC
= Pin 14
GND = Pin 7
SF00713
SF00714
1995 Sep 22
2
853-0348 15794
Philips Semiconductors
Product specification
8-bit serial-in parallel-out shift register
74F164
LOGIC DIAGRAM
Dsa
Dsb
1
2
D
Q
CP
RD
8
D
Q
CP
RD
D
Q
CP
RD
D
Q
CP
RD
D
Q
CP
RD
D
Q
CP
RD
D
Q
CP
RD
D
Q
CP
RD
CP
MR 9
V
CC
= Pin 14
GND = Pin 7
3
Q0
Q1
4
Q2
5
Q3
6
10
Q4
11
Q5
12
Q6
13
Q7
SF00715
FUNCTION TABLE
INPUTS
MR
L
H
H
H
H
H
h
L
l
qn
X
↑
=
=
=
=
=
=
=
CP
X
↑
↑
↑
↑
Dsa
X
l
l
h
h
Dsb
X
l
h
l
h
Q0
L
L
L
L
H
Q1
L
q0
q0
q0
q0
Q2
L
q1
q1
q1
q1
OUTPUTS
Q3
L
q2
q2
q2
q2
Q4
L
q3
q3
q3
q3
Q5
L
q4
q4
q4
q4
Q6
L
q5
q5
q5
q5
Q7
L
q6
q6
q6
q6
Shift
Reset (Clear)
OPERATING MODE
High voltage level
High voltage level one setup time prior to the Low-to-High clock transition.
Low voltage level
Low voltage level one setup time prior to the Low-to-High clock transition.
Lower case letter indicate the state of the referenced output one setup time prior to the Low-to-High clock transition.
Don’t care
Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
b
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Commercial Range
Operating free-air tem erature range
temperature
O erating
Storage temperature range
Industrial Range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–40 to +85
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMIT
SYMBOL
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
T
amb
b
Supply voltage
High-level iput voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Commercial Range
O erating
Operating free-air tem erature range
temperature
Industrial Range
0
–40
PARAMETER
MIN
4.5
2.0
0.8
–18
–1
20
+70
+85
NOM
5.0
MAX
5.5
UNIT
V
V
V
mA
mA
mA
°C
1995 Sep 22
3
Philips Semiconductors
Product specification
8-bit serial-in parallel-out shift register
74F164
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
TEST
SYMBOL
PARAMETER
CONDITIONS
1
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OH
= MAX
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
-60
33
MIN
LIMITS
TYP
2
MAX
V
3.4
0.30
0.30
–0.73
0.50
0.50
–1.2
100
20
–0.6
–150
55
V
V
V
V
µA
µA
mA
mA
mA
UNIT
V
OH
V
OL
High-level out ut voltage
output
Low-level output voltage
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.5
2.7
V
IK
I
I
I
IH
I
ILL
I
OS
I
CC
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Short-circuit output current
3
Supply current (total)4
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter test, I
OS
tests should be performed last.
4. Measure I
CC
with the serial inputs grounded, the clock input at 2.4V, and a momentary ground, then applied to Master Reset, and all outputs
open.
APPLICATION
RESET
CLOCK
CP
DATA
ENABLE
Dsa
74F164
Dsb
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
H
Dsb
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MR
Dsa
74F164
CP
MR
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
The 74F164 can be cascaded to form synchronous shift registers of longer length.
Here, two devices are combined to form a 16-bit shift register.
SF00716
1995 Sep 22
4
Philips Semiconductors
Product specification
8-bit serial-in parallel-out shift register
74F164
AC ELECTRICAL CHARACTERISTICS
LIMITS
TEST
CONDITION
T
amb
= +25°C
+25 C
V
CC
= 5V
C
L
= 50pF
R
L
= 500Ω
MIN
f
max
t
PLH
t
PHL
t
PHL
Maximum clock frequency
Propagation delay
CP to Qn
Propagation delay
MR to Qn
Waveform 1
Waveform 1
Waveform 3
80
3.0
5.0
5.5
TYP
100
5.0
7.0
7.5
8.0
10.0
10.5
MAX
T
amb
= 0°C to +70°C
0 C +70 C
V
CC
= +5V±10%
C
L
= 50pF
R
L
= 500Ω
MIN
80
2.5
5.0
5.5
9.0
11.0
11.5
MAX
T
amb
= –40°C to +85°C
40 C +85 C
V
CC
= +5V±10%
C
L
= 50pF
R
L
= 500Ω
MIN
80
2.5
5.0
5.5
9.0
11.0
11.5
MAX
MHz
ns
ns
SYMBOL
PARAMETER
UNIT
AC SETUP REQUIREMENTS
LIMITS
TEST
CONDITION
T
amb
= +25°C
+25 C
V
CC
= 5V
C
L
= 50pF
R
L
= 500Ω
MIN
t
s
(H)
t
S
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
REC
Setup time, High or Low
D
n
to CP
Hold time, High or Low
D
n
to CP
CP Pulse width
High or Low
MR Pulse wicth
Low
Recovery time
MR to CP
Waveform 2
Waveform 2
Waveform 1
Waveform 3
Waveform 3
7.0
7.0
1.0
1.0
4.0
7.0
7.0
7.0
TYP
MAX
T
amb
= 0°C to +70°C
0 C +70 C
V
CC
= +5V±10%
C
L
= 50pF
R
L
= 500Ω
MIN
7.0
7.0
2.0
2.0
4.0
7.0
7.0
7.0
MAX
T
amb
= –40°C to +85°C
40 C +85 C
V
CC
= +5V±10%
C
L
= 50pF
R
L
= 500Ω
MIN
7.0
7.0
2.0
2.0
4.0
7.0
7.0
7.0
MAX
ns
ns
ns
ns
ns
SYMBOL
PARAMETER
UNIT
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
max
MR
CP
V
M
t
w
(H)
t
PHL
V
M
t
w
(L)
t
PLH
V
M
CP
t
PHL
V
M
V
M
t
w
(L)
t
REC
V
M
V
M
V
M
Qn
SF00294
Qn
Waveform 1. Propagation delay for Clock input to output,
Clock Pulse width, and maximum Clock frequency
V
M
SF00158
Waveform 3. Master Reset pulse width, Master Reset to output
delay and Master Reset to Clock recovery time
Dn
V
M
t
s
(H)
CP
V
M
t
h
(H)
V
M
t
s
(L)
V
M
t
h
(L)
V
M
V
M
SF00191
Waveform 2. Data setup and hold times
1995 Sep 22
5
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