74ALVC16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
October 2001
Revised May 2005
74ALVC16373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
outputs are in a high impedance state.
The 74ALVC16373 is designed for low voltage (1.1V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.1V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
(I
n
to O
n
)
3.5 ns max for 3.0V to 3.6V V
CC
3.9 ns max for 2.3V to 2.7V V
CC
6.8 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Support live insertion and withdrawal (Note 1)
s
Uses patented noise/EMI reduction circuitry
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC16373GX
(Note 2)
74ALVC16373MTD
(Note 3)
Package Number
BGA54A
(Preliminary)
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2:
BGA package available in Tape and Reel only.
Note 3:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500687
www.fairchildsemi.com
74ALVC16373
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Names
OE
n
LE
n
I
0
–I
15
O
0
–O
15
NC
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
No Connect
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
O
0
O
2
O
4
O
6
O
8
O
10
O
12
O
14
O
15
2
NC
O
1
O
3
O
5
O
7
O
9
O
11
O
13
NC
3
OE
1
NC
V
CC
GND
GND
GND
V
CC
NC
OE
2
4
LE
1
NC
V
CC
GND
GND
GND
V
CC
NC
LE
2
5
NC
I
1
I
3
I
5
I
7
I
9
I
11
I
13
NC
6
I
0
I
2
I
4
I
6
I
8
I
10
I
12
I
14
I
15
Truth Tables
Inputs
LE
1
X
H
Pin Assignment for FBGA
H
L
OE
1
H
L
L
L
Inputs
LE
2
X
H
H
L
H
L
X
Z
O
0
Outputs
I
0
–I
7
X
L
H
X
O
0
–O
7
Z
L
H
O
0
Outputs
I
8
–I
15
X
L
H
X
O
8
–O
15
Z
L
H
O
0
OE
2
H
L
L
L
(Top Thru View)
HIGH Voltage Level
LOW Voltage Level
Immaterial (HIGH or LOW, inputs may not float)
High Impedance
Previous O
0
before HIGH-to-LOW of Latch Enable
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2
74ALVC16373
Functional Description
The 74ALVC16373 contains sixteen edge D-type latches
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LE
n
) input is HIGH, data on
the I
n
enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
its I input changes. When LE
n
is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LE
n
. The
3-STATE outputs are controlled by the Output Enable
(OE
n
) input. When OE
n
is LOW the standard outputs are in
the 2-state mode. When OE
n
is HIGH, the standard outputs
are in the high impedance mode but this does not interfere
with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74ALVC16373
Absolute Maximum Ratings
(Note 4)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 5)
DC Input Diode Current (I
IK
)
V
I
0V
DC Output Diode Current (I
OK
)
V
O
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
0.5V to
4.6V
0.5V to 4.6V
0.5V to V
CC
0.5V
50 mA
50 mA
r
50 mA
r
100 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 6)
Power Supply
Operating
Input Voltage (V
I
)
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
t/
'
V)
V
IN
0.8V to 2.0V, V
CC
3.0V
10 ns/V
Note 4:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 5:
I
O
Absolute Maximum Rating must be observed.
Note 6:
Floating or unused inputs must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
40
q
C to
85
q
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 -1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
CC
- 0.2
1.2
2
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
V
V
V
V
Max
Units
100
P
A
4 mA
6 mA
12 mA
1.65 - 3.6
1.65
2.3
2.3
2.7
3.0
I
OH
V
OL
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
OL
I
I
I
OZ
I
CC
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in I
CC
per Input
24 mA
100
P
A
4 mA
6 mA
12mA
24 mA
3.0
1.65 - 3.6
1.65
2.3
2.3
2.7
3
3.6
3.6
0
3.6
3 -3.6
0
d
V
I
d
3.6V
0
d
V
O
d
3.6V
V
I
V
IH
V
CC
or GND, I
O
V
CC
0.6V
r
5.0
r
10
40
750
P
A
P
A
P
A
P
A
'
I
CC
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4
74ALVC16373
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
Min
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
Propagation Delay
Bus to Bus
Propagation Delay
LE to Bus
Output Enable Time
Output Disable Time
1.3
1.3
1.3
1.3
C
L
3.3V
r
0.3V
Max
3.5
3.5
4.0
4.0
50 pF
V
CC
Min
1.5
1.5
1.5
1.5
2.7V
Max
3.9
4.4
5.1
4.3
V
CC
Min
1.0
1.0
1.0
1.0
40
q
C to
85
q
C, R
L
500
:
C
L
2.5V
r
0.2V
Max
3.4
3.9
4.6
3.8
30 pF
V
CC
Min
1.5
1.5
1.5
1.5
1.8V
r
0.15V
Max
6.8
7.8
9.2
6.8
ns
ns
ns
ns
Units
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Parameter
V
I
V
I
Outputs Enabled f
0V or V
CC
0V or V
CC
10 MHz, C
L
50 pF
Conditions
T
A
V
CC
3.3
3.3
3.3
2.5
25
q
C
Typical
6
7
20
20
Units
pF
pF
pF
5
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