74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs
January 1990
Revised November 1999
74ACTQ533
Quiet Series Octal Transparent Latch
with 3-STATE Outputs
General Description
The ACTQ533 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data satisfying the input tim-
ing requirements is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high impedance state.
The ACTQ533 utilizes Fairchild Quiet Series technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series features GTO
output control and undershoot corrector in addition to a
split ground bus for superior performance.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch up immunity
s
Eight latches in a single package
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs source/sink 24 mA
s
Inverted version of the ACTQ373
s
4 kV minimum ESD immunity
Ordering Code:
Order Number
74ACTQ533SC
74ACTQ533MTC
74ACTQ533PC
Package Number
M20B
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
© 1999 Fairchild Semiconductor Corporation
DS010630
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74ACTQ533
Truth Table
Inputs
LE
X
H
H
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Outputs
D
n
X
L
H
X
O
n
Z
H
L
O
0
OE
H
L
L
L
Functional Description
The ACTQ533 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs at setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE standard outputs are con-
trolled by the Output Enable (OE) input. When OE is LOW,
the standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ACTQ533
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latchup Source
or Sink Current
Junction Temperature (T
J
)
PDIP
140°C
±
300 mA
±
50 mA
−
65°C to
+
150°C
±
50 mA
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
−
20 mA
+
20 mA
−0.5V
to V
CC
+
0.5V
−
0.5V to
+
7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
∆V/∆t
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum
I
CC
/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
1.1
−0.6
1.9
4.0
1.5
−1.2
2.2
0.6
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
±0.25
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
±2.5
1.5
75
−75
40.0
µA
µA
mA
mA
mA
µA
V
V
V
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 2)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Figures 1, 2
(Note 4)(Note 5)
Figures 1, 2
(Note 4)(Note 5)
(Note 4)(Note 6)
3
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74ACTQ533
DC Electrical Characteristics
Symbol
V
ILD
Parameter
Maximum LOW Level
Dynamic Input Voltage
V
CC
(V)
5.0
(Continued)
T
A
= +25°C
Typ
1.2
0.8
T
A
= −40°C
to
+85°C
Guaranteed Limits
V
(Note 4)(Note 6)
Units
Conditions
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
DIP package.
Note 5:
Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6:
Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
),
f
=
1 MHz.
AC Electrical Characteristics
V
CC
Symbol
Parameter
(V)
(Note 7)
t
PHL
t
PLH
t
PHL
t
PLH
t
PZL
, t
PZH
t
PHZ
, t
PLZ
t
OSHL
t
OSLH
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
Output to Output Skew
D
n
to O
n
(Note 8)
5.0
5.0
5.0
5.0
5.0
Min
2.0
2.5
2.0
1.0
T
A
= +
25°C
C
L
=
50 pF
Typ
6.0
7.0
7.0
8.0
0.5
Max
8.0
9.0
9.0
10.0
1.0
T
A
= −
40°C to
+
85°C
C
L
=
50 pF
Min
2.0
2.5
2.0
1.0
Max
8.5
9.5
9.5
10.5
1.0
ns
ns
ns
ns
ns
Units
Note 7:
Voltage Range 5.0 is 5.0V
±
0.5V.
Note 8:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
AC Operating Requirements
V
CC
Symbol
Parameter
(V)
(Note 9)
t
S
t
H
t
W
Setup Time, HIGH or LOW
D
n
to LE
Hold Time, HIGH or LOW
D
n
to LE
LE Pulse Width, HIGH
Note 9:
Voltage Range 5.0 is 5.0V
±
0.5V.
T
A
= +
25°C
C
L
=
50 pF
Typ
0
0
2.0
3.0
1.5
4.0
T
A
= −
40°C to
+
85°C
C
L
=
50 pF
Guaranteed Minimum
3.0
1.5
4.0
ns
ns
ns
Units
5.0
5.0
5.0
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
40
Units
pF
pF
V
CC
=
OPEN
V
CC
=
5.0V
Conditions
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4
74ACTQ533
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
scope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with a digital volt meter.
Tektronics Model 7854 Oscillo-
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
• Next decrease the input HIGH voltage level on the V
IH
until the output begins to oscillate or steps out a min of 2
ns. Oscillation is defined as noise on the output LOW
level that exceeds V
IL
limits, or on output HIGH levels
that exceed V
IH
limits. The input HIGH voltage level at
which oscillation occurs is defined as V
IHD
.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 10:
V
OHV
and V
OLP
are measured with respect to ground reference.
Note 11:
Input pulses have the following characteristics:
f
=
1 MHz, t
r
=
3 ns, t
f
=
3 ns, skew
<
150 ps.
FIGURE 2. Simultaneous Switching Test Circuit
5
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