74HC574-Q100; 74HCT574-Q100
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 1 — 2 August 2012
Product data sheet
1. General description
The 74HC574-Q100; 74HCT574-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC
standard no. 7A.
The 74HC574-Q100; 74HCT574-Q100 are octal D-type flip-flops featuring separate
D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock
(CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops store
the state of their individual D-inputs that meet the set-up and hold times requirements on
the LOW-to-HIGH CP transition. When OE is LOW the contents of the 8 flip-flops are
available at the outputs. When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the state of the flip-flops.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3-state non-inverting outputs for bus-oriented applications
8-bit positive, edge-triggered register
Common 3-state output enable input
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74HC574-Q100; 74HCT574-Q100
Octal D-type flip-flop; positive edge-trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC574D-Q100
74HCT574D-Q100
74HC574PW-Q100
74HCT574PW-Q100
40 C
to +125
C
TSSOP20
40 C
to +125
C
SO20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT360-1
Type number
4. Functional diagram
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
FF1
to
FF8
3-STATE
OUTPUTS
Q0 19
Q1 18
Q2 17
Q3 16
Q4 15
Q5 14
Q6 13
Q7 12
11 CP
1 OE
mna800
Fig 1.
Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
CP
FF2
FF3
FF4
FF5
FF6
FF7
FF8
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aah077
Fig 2.
Logic diagram
74HC_HCT574_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
2 of 17
NXP Semiconductors
74HC574-Q100; 74HCT574-Q100
Octal D-type flip-flop; positive edge-trigger; 3-state
11
1
11
2
3
4
5
6
7
8
9
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
mna798
C1
EN
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
8
9
3
4
5
6
7
1D
19
18
17
16
15
14
13
12
mna446
Fig 3.
Logic symbol
Fig 4.
IEC logic symbol
5. Pinning information
5.1 Pinning
+&4
+&74
2(
'
'
'
'
'
'
'
'
9
&&
4
4
4
4
4
4
4
4
&3
DDD
+&4
+&74
2(
'
'
'
'
'
'
'
'
9
&&
4
4
4
4
4
4
4
4
&3
DDD
*1'
*1'
Fig 5.
Pin configuration SO20
Fig 6.
Pin configuration TSSOP20
74HC_HCT574_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
3 of 17
NXP Semiconductors
74HC574-Q100; 74HCT574-Q100
Octal D-type flip-flop; positive edge-trigger; 3-state
5.2 Pin description
Table 2.
Symbol
OE
D[0:7]
GND
CP
Q[0:7]
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
20
Description
3-state output enable input (active LOW)
data input
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
supply voltage
19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output
6. Functional description
Table 3.
Function table
[1]
Input
OE
Load and read register
Load register and disable output
L
L
H
H
[1]
H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition;
Z = high-impedance OFF-state;
= LOW-to-HIGH clock transition.
Operating mode
CP
Dn
l
h
l
h
Internal
flip-flop
L
H
L
H
Output
Qn
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
[1]
Max
+7
20
20
35
+70
70
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
-
For SO20 packages: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP20 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
74HC_HCT574_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
4 of 17
NXP Semiconductors
74HC574-Q100; 74HCT574-Q100
Octal D-type flip-flop; positive edge-trigger; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC574-Q100
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT574-Q100
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC574-Q100
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
6.0
mA; V
CC
= 4.5 V
I
O
=
7.8
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 6.0 mA; V
CC
= 4.5 V
I
O
= 7.8 mA; V
CC
= 6.0 V
I
I
I
OZ
input leakage
current
OFF-state
output current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
IH
or V
IL
;
V
O
= V
CC
or GND;
V
CC
= 6.0 V
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
0.1
0.1
0.1
0.26
0.26
0.1
0.5
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1.0
5.0
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
10.0
V
V
V
V
V
A
A
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
74HC_HCT574_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
5 of 17
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