Application Note AN-N13
VPI/VCI Translation and Cell Tagging in
ATM with the MU9C4320L ATMCAM
TM
INTRODUCTION
The MU9C4320L ATMCAM is a 4K x 32 content-
addressable memory (CAM) with a 32-bit wide data interface.
The device is designed for use in ATM switches and routers
to provide very high throughput VPI/VCI translation.
VPI/VCI fields from the ATM cell header are compared
against a list of current connections stored in the ATMCAM
array. As a result of the comparison, the ATMCAM
generates an address that is used to access an external RAM
where VPI/VCI mapping data and other information
associated with the connection are stored.
Ø
Ø
Ø
Ø
Fully deterministic translation time, independent
from the size of the list, and the length of VPI/VCI
Automatic full VPI/VCI or VPI only translation
without extra cycle
Fast connection addition/deletion
No limitation in terms of associated information to
each connection.
ATM APPLICATIONS
VPI/VCI Translation
ATM global data exchange is based on a succession of
point-to-point connections. Each of the connections is
identified by a Virtual Path Identifier (VPI)/Virtual Channel
Identifier (VCI) combination, which can be found in the
header of all ATM cells carrying information for a specific
connection.
At the User-Network Interface (UNI), the VPI is an 8-bit
field and the VCI is a 16-bit field in the cell header, while at
the Network-Network Interface (NNI) the VPI is a 12-bit field
and the VCI a 16-bit field.
A VCI/VPI value strictly has local significance. Each segment
of a total connection over several switches has unique
VPI/VCI combinations for each segment of the connection,
either from user to switch or from switch to switch. This
implies that whenever an ATM cell travels through a switch,
the VPI/VCI value has to be changed into the value used for
the next part of the connection. This process is called
VPI/VCI translation.
Various solutions can be implemented to perform such
translations. Using the MU9C4320L ATMCAM is the most
efficient solution and provides the following advantages:
Ø
No limitation of the range of legal values for
VPI/VCI, a guarantee for full interoperability
Cell Tagging
In most switch implementations, the VPI/VCI translation is
performed at the moment the ATM cells have been received
by the switch port. In many designs, in addition to the
VPI/VCI translation, the cells are tagged with information
to route them through the switch. The cell tagging process
can be handled by the ATMCAM during the VPI/VCI
translation, without time penalty.
Policing
Besides VPI/VCI translation and cell tagging, a switch port
may have to perform more functions which can be assisted
by the ATMCAM. One of these functions is policing. With
the help of the ATMCAM, the switch is able to check
whether the VPI/VCI is known and a VPI/VCI translation
and tagging operation can take place, or whether the cell
should be discarded due to an unknown VPI/VCI.
The amount of cells that are allowed to come in during a
certain time frame is based upon the bandwidth allocation
for that specific connection. The average bandwidth and
burstiness of the incoming cells for a connection have to
conform to certain rules. If these rules are violated the switch
could decide to drop the extra cells from that specific
connection.
Alternatively those extra cells can still be forward by the
switch. In such cases, their Cell Lose Priority bit (CLP) is
updated. This field is part of each ATM cell header, and
indicates if the cell is or is not within the negotiated
bandwidth for the connection and its relative priority. If a
burst of data traffic is happening and a specific switch is
saturated, cells with a low priority will be dropped. Checking
the value of the CLP field while processing the VPI/VCI
MUSIC Semiconductors, the MUSIC logo, and the phrase “MUSIC Semiconductors”
are registered trademarks of MUSIC Semiconductors. MUSIC and ATMCAM are
trademarks of MUSIC Semiconductors.
30 September 1998 Rev. 0a
AN-N13
translation is easily done with the MU9C4320L, without
requiring an extra cycle. It should be mentioned that this
allows easy management of the incoming frame buffer in a
“Find and Replace” mode.
The UTOPIA interface accepts cell data from a PHY device
through the Cell Input interface. Transfer of cell data begins
with the PHY device indicating it has data available for
transfer by asserting the RxEmpty signal. Data is transferred
over RxData15–0 in 16-bit quantities in each cycle following
an assertion of RxEnb by the UTOPIA interface. Also
transferred are RxSOC, the Start Of Cell indicator, and RxPrty,
which provides odd parity over the 16-bit data bus.
Cell data is transferred from the UTOPIA interface to a
downstream ATM Layer entity, such as the switch fabric or
another UTOPIA interface, utilizing the Cell Output interface.
The UTOPIA interface acts as a PHY device on the UTOPIA
bus during transfer. Data is transferred over TxData15–0 in
16-bit quantities in each cycle following an assertion of TxEnb
SYSTEM BLOCK DIAGRAM
ATMCAM Controller
A wide variety of interfaces between ICs is found in the
market today, not only varying in speed and type of
information carried, but also varying in width. A possible
ATM system is depicted in Figure 1. In this example system,
a 16-bit wide UTOPIA (Level 2) interface (Cell Input and Output)
is used.
M e m or y I n te r fa c e
A s s o c ia t e d
CAM
R x C la v
Rx D at a 15 - 0
Rx P r t y
R x S OC
Rx E n b
R x C lk
C o n f i g u r a ti o n
R e g is t e r s
Ce l l B u f f er
Tx C l k
C e ll
In p u t
Ce l l D at a
C e ll
Ou t p u t
Tx S O C
Tx E n b
C o m pa r a nd
He ad e r
E x tr a c t
He ad e r
R e pl a c e
Tx D a ta 1 5 -0
Tx P r ty
Da t a
Tx C l a v
Loc a l In t e r f a c e
Figure 1: ATMCAM Controller, Block Diagram
/ FI , / M I ,
/R ES ET , /C S 2
MU 9 C 4 3 2 0 L – 7 0
ATMCAM
(4 K X 3 2 )
P A0
A A1 1 -0
DQ 3 1 – 0, / V B
S RAM
(3 2 K X 3 2 )
A1 4
A1 3 – 2
A1 – 0
/O E, /E, /C S1 ,
/ W , AC 1 1 - 0 , / A V
/ F F, / M F ,
/M M , /M V
A D P 1 , AD P 0
W , /C S , /O E
Me m o r y I n te r fa c e
Figure 2: Memory Interface
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2
AN-N13
by the controlling entity on the UTOPIA bus. Also
transferred are TxSOC, the Start Of Cell indicator, and TxPrty,
which provides odd parity over the 16-bit data bus.
Memory Interface
In Figure 2, the Memory interface is shown more precisely.
The VPI/VCIs and VPIs are stored in the 70ns ATMCAM
(MU9C4320L–70), associated data (new VPI/VCI or VPI and
tagging information) is stored in a SRAM. 4K VPI/VCIs and
4K VPIs require 8K of SRAM containing the associated
data. It is assumed that 128 bits of associated data per
connection are required, so a 1Mb SRAM (8Kx128) is
needed. Since 32-bit can be considered as a standard
buswidth, in this example a 32K x 32 SRAM is used. This
implies that the associated datafield has to be read out in
four 32-bit parts.
The Page address of the ATMCAM or the VP Table is
present on the PA bus. By choosing the Page addresses
such that they only differ one bit (e.g. PA of the ATMCAM
is 0000B and PA of the VP Table is 0001B) only one line of
the PA bus has to be connected to the SRAM. In this example
PA0 of the ATMCAM is used to address the SRAM and is
therefore connected to A14 of the SRAM. When PA0 is “0”
(ATMCAM), the first 16K of the SRAM are addressed and
when PA0 is “1” (VP Table) the second part of 16K is
addressed.
The AA bus presents the address of the matching location
in the ATMCAM, or in case of a VPI match, the VP Table
address. The AA bus is connected to the A13–A2 pins of
the Address bus of the SRAM. By toggling the two least
significant bits of the Address bus (A0 and A1) with external
logic (or a burst counter internal to the SRAM), the
associated data can be read out in four 32-bit parts.
An ATMCAM lookup requires 70ns (MU9C4320L–70).
When using a standard 50MHz clock, it takes four 20ns
clock cycles to perform a VPI/VCI lookup. To obtain maximum
performance the lookup of associated data has to take place
while the next ATMCAM lookup is performed. This implies
each read operation of 32 bits of associated data has to be
done within a 20ns clock cycle.
ATMCAM OPERATIONS
The flowcharts and code in this section are examples of the
basic ATM operations in addition to the initialization of the
ATMCAM:
Ø
Ø
Ø
Ø
Ø
Ø
VPI/VCI lookup
VPI lookup
VPI/VCI addition
VPI addition
VPI/VCI removal
VPI removal
!HARDWARE RESET
!MU9C4320 is in SW-mode
WR FR {MR000}
0x00FFF100
!MU9C4320 is programmed to HW-mode
!lowest priority CAM
!VP-table enabled
!VP PA is 1H
!PA is OH
WR DS {MR000}
!disable Device Select register CS
WR MR001
!Mask register 1 for VPI/VCI
WR MR002
!Mask register 2 for VPI
/AV=HIGH
/AV=HIGH
/W=LOW
/W=LOW
0x00000100
/AV=HIGH
0x0000000F
/AV=HIGH
0x000FFFFF
/AV=HIGH
Figure 3: INIT.DAT, Initialization Code Listing
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Rev. 0a
AN-N13
The format of the routines shown if the Code listings are as
follows:
first column
second column
third column
: command on the AC bus
: data on the DQ bus
: the state of the AV pin
lowest-priority ATMCAM, enable the VP Table, set the VP
Page address to 1H, and set the ATMCAM Page address to 0H.
Lookup
The VPI/VCI lookup is done in routine LOOKUP.DAT,
shown in Figure 5 (flowchart in Figure 4). At the end of this
routine the flags /MV and /MF indicate whether a match
occurred or not and if so what kind of match it is. For a
VPI/VCI matching, the matching address will be present on
the AA bus, the PA bus will present the PA of the ATMCAM
(0H). If there was a match in the VP Table and not in the
ATMCAM the matching VP Table address will be present
on the AA bus, the PA bus will present the PA of the VP
Initialization
The initialization routine shown in Figure 3 is called
INIT.DAT. After a hardware reset the ATMCAM is in
software mode. First the ATMCAM has to be programmed
into hardware mode. The first two instructions take care of
this. These two instructions also program the device as
Co m p a r e V P I / V C I
o n D Q - b u s w it h
CA M - e n t r i e s
HI G H
/ FF
LO W
HI G H
/M V
LO W
Com pa re V P I/V CI
on D Q -b us
W r ite to CR
CAM is f ull
/M F
/M V
LO W
HI G H
(V P I M a tc h )
LO W
(V P I / V C I M a t c h )
HI G H
HI G H
(M a tc h in V P -ta bl e )
LO W
/M F
NO M a t c h
pu r g e c e l l
u s e H P M A o n P A :A A b u s
to g e t a s s o c i a t e d d a ta
fr o m S R A M
M a tc h in CAM
V P I/V CI a lr e a d y
lis t e d (ER RO R )
upda te RAM
loc a tion(s ) w ith
a s s oc ia te d da ta
M ove CR t o Ne x t
Fr e e Addr e s s
Figure 4: Lookup Flowchart
CMP DQ {MR001}
!compare VPI/VCI
VPI/VCI
/AV=HIGH
Figure 7 : Add a VPI/VCI-connection
Figure 5: Lookup.Dat, VPI/VCI Lookup Code Listing
CMPW DQ {MR001}VPI/VCI
/AV=HIGH
!compare VPI/VCI and write it to CR
MOV [NFA], CR {MR001}
/AV=HIGH
!move the content of CR to the Next Free Address
CMP DQ{MR002}
!compare only VPI
VPI
/AV=HIGH
Figure 8: ADD.DAT, Add a VPI/VCI-connection
Code Listing
Figure 6: VPI Lookup Code Listing
Rev. 0a
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AN-N13
Table (1H). The SRAM can be addressed by a combination
of the PA bus, AA bus, and some external logic to read out
associated data. If a lookup on only the VPI is required, use
MR002 instead of MR001 and write the VPI on the DQ bus
(see Figure 6).
Adding a Connection
To add a VPI/VCI to the list in the ATMCAM, the routine
ADD.DAT is used. This routine is shown in Figure 8
(flowchart in Figure 7). It first compares the VPI/VCI to be
added. In this example switching on VPI/VCI is allowed also
if the VPI of this connection is already set in the VP Table
(so it is possible to switch separate VCIs of a VPI
connection). This means a VPI/VCI connection can be added
when it is not found in the ATMCAM. To add the VPI/VCI
WR AR {MR000}
!write VPI to AR
VPI
/AV=HIGH
it is moved from the Comparand register to the Next Free
address. This NFA becomes available at the PA:AA bus, so
the SRAM can be addressed to write the associated data
into it.
To add a VPI the routine used is ADD_VPI.DAT, which is
shown in Figure 9. First a lookup on the VPI is performed.
Since in this example it is possible to switch certain VCIs
separate from a VPI connection, the VPI is added if it is not
already set. In other systems where it is not allowed to switch
on separate VCIs, the decision to add the VPI and delete the
VPI/VCIs conflicting with this VPI can be taken by external
logic, as shown in Figure 10. Addition of the VPI is done by
writing the VPI to the Address register, after which the
corresponding VP Table address is set.
Com pa r e V P I/V CI
on D Q -b us
SET VP@[AR]
!set VP Table bit at AR-location
/AV=HIGH
Re s e t v a lidit y-bit of
m a tc hing loc a tion
Figure 9: Add_VPI.DAT. Add a VPI connection
Code Listing
Figure 11: Delete a VPI/VCI connection
CMP DQ {MR001}
!compare VPI/VCI
C o mp are VPI
o n D Q -b us
VPI/VCI /AV=HIGH
RST V@[HPM]
/AV=HIGH
!reset validity-bit at Highest Priority Matching location
Figure 12: DELETE.DAT, Delete a VPI/VCI connection
Code Listing
W r ite V P I to
Addr e s s Re gis te r
/MV
HIG H
LOW
LOW
(Ma tch in C AM)
/MF
VP-tab le
b it a lre ad y se t
Re s e t v a lidit y-bit of
a ddr e s s loc a tion
u pd ate R AM
lo catio n(s) with
a sso cia te d da ta
Figure13: Delete a VPI connection
Se t VP-ta b le b it
WR AR{MR000}
!write VPI to AR
VPI
/AV=HIGH
RST V@[AR]
!reset VP table bit at AR-location
Figure 10: Alternative Method to Add
a VPI connection
/AV=HIGH
Figure 14: Delete_VPI.DAT, Delete a VPI connection
Code listing
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