74AHCU04-Q100
Hex unbuffered inverter
Rev. 1 — 5 June 2013
Product data sheet
1. General description
The 74AHCU04 is high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.
The 74AHCU04 is a general-purpose hex unbuffered inverter. Each of the six inverters is
a single stage.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Low power dissipation
Balanced propagation delays
Inputs accept voltages higher than V
CC
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74AHCU04D-Q100
Name
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
40 C
to +125
C
SO14
74AHCU04PW-Q100
40 C
to +125
C
TSSOP14
74AHCU04BQ-Q100
40 C
to +125
C
DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
NXP Semiconductors
74AHCU04-Q100
Hex unbuffered inverter
4. Functional diagram
1
1
2
1
1A
1Y
2
3
1
4
3
2A
2Y
4
5
1
6
5
3A
3Y
6
9
1
8
9
4A
4Y
8
11
5A
5Y
10
11
1
10
13
6A
6Y
12
13
1
mna343
12
A
Y
mna045
mna342
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one
inverter)
5. Pinning information
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
74AHCU04_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
2 of 15
NXP Semiconductors
74AHCU04-Q100
Hex unbuffered inverter
5.1 Pin description
Table 2.
Symbol
1A, 2A, 3A, 4A, 5A, 6A
1Y, 2Y, 3Y, 4Y, 5Y, 6
GND
V
CC
Pin description
Pin
1, 3, 5, 9, 11, 13
2, 4, 6, 8, 10, 12
7
14
Description
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level
Input
nA
L
H
Output
nY
H
L
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
I
IK
V
I
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V
[1]
Min
0.5
20
0.5
-
-
-
75
65
Max
+7.0
-
+7.0
20
25
75
-
+150
500
Unit
V
mA
V
mA
mA
mA
mA
C
mW
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For TSSOP14 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
74AHCU04_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
3 of 15
NXP Semiconductors
74AHCU04-Q100
Hex unbuffered inverter
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 3.3 V
0.3 V
V
CC
= 5.0 V
0.5 V
Conditions
Min
2.0
0
0
40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
Unit
V
V
V
C
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol
V
IH
Parameter
HIGH-level
input voltage
Conditions
Min
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
50 A;
V
CC
= 2.0 V
I
O
=
50 A;
V
CC
= 3.0 V
I
O
=
50 A;
V
CC
= 4.5 V
1.7
2.4
4.4
-
-
-
1.8
2.7
4.0
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3
25
C
Typ
Max
-
-
-
0.3
0.6
1.1
-
-
-
-
-
0.2
0.3
0.5
0.36
0.36
0.1
2.0
10
40 C
to +85
C
Min
1.7
2.4
4.4
-
-
-
1.8
2.7
4.0
2.48
3.8
-
-
-
-
-
-
-
-
-
-
-
0.3
0.6
1.1
-
-
-
-
-
0.2
0.3
0.5
0.44
0.44
1.0
20
10
Max
40 C
to +125
C
Unit
Min
1.7
2.4
4.4
-
-
-
1.8
2.7
4.0
2.4
3.7
-
-
-
-
-
-
-
-
-
-
-
0.3
0.6
1.1
-
-
-
-
-
0.2
0.3
0.5
0.55
0.55
2.0
40
10
Max
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
pF
I
O
=
4.0
mA; V
CC
= 3.0 V 2.58
I
O
=
8.0
mA; V
CC
= 4.5 V 3.94
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
A;
V
CC
= 2.0 V
I
O
= 50
A;
V
CC
= 3.0 V
I
O
= 50
A;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
-
-
-
-
-
-
-
-
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
74AHCU04_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
4 of 15
NXP Semiconductors
74AHCU04-Q100
Hex unbuffered inverter
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see
Figure 7.
Symbol
t
pd
Parameter
propagation
delay
Conditions
Min
nA to nY; see
Figure 6
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF
C
L
= 50 pF
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF
C
L
= 50 pF
C
PD
power
dissipation
capacitance
C
L
= 50 pF; f
i
= 1 MHz;
V
I
= GND to V
CC
[4]
[3]
[1]
[2]
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
-
-
-
-
-
3.0
3.4
2.4
3.5
9.1
7.1
10.6
5.5
7.0
-
1.0
1.0
1.0
1.0
-
8.5
12.0
6.5
8.0
-
1.0
1.0
1.0
1.0
-
9.0
13.5
7.0
9.0
-
ns
ns
ns
ns
pF
[1]
[2]
[3]
[4]
t
pd
is the same as t
PLH
and t
PHL
.
Typical values are measured at V
CC
= 3.3 V.
Typical values are measured at V
CC
= 5.0 V.
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC2
f
i
N +
(C
L
V
CC2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC2
f
o
) = sum of outputs.
11. Waveforms
V
I
nA input
GND
t
PHL
V
OH
nY output
V
OL
V
M
V
M
mna344
V
M
V
M
V
CC
t
PLH
PULSE
GENERATOR
VI
VO
DUT
RT
CL
50 pF
mna034
V
M
= 0.5
V
CC
; V
I
= GND to V
CC
.
Test data is given in
Table 7.
Definitions for test circuit:
C
L
= Load capacitance including jig and probe
capacitance.
R
T
= Termination resistance should be equal to output
impedance Z
o
of the pulse generator.
Fig 6.
The input (nA) to output (nY) propagation
delay times
Fig 7.
Test circuit for measuring switching times
74AHCU04_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 5 June 2013
5 of 15
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