14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Features
One input to 14 output Buffer/Driver
Supports up to three SDRAM DIMMs
Two additional outputs for feedback
Serial interface for output control
Low skew outputs
Up to 133MHz operation
Multiple V
DD
and V
SS
pins for noise reduction
Dedicated OE pin for testing
Low EMI outputs
28 Pin SOIC (300-mil) package
3.3V operation
Functional Description
The ASM2I2314ANZ is a 3.3V buffer designed to distribute
high-speed clocks in desktop PC applications. The part has
14 outputs, 12 of which can be used to drive up to three
SDRAM DIMMs, and the remaining can be used for
external feedback to a PLL. The device operates at 3.3V
and outputs can run up to 133MHz, thus making it
compatible
with
Pentium
®*
II
processors.
The
ASM2I2314ANZ can be used in conjunction with the clock
synthesizer for a complete Pentium II motherboard
solution. The ASM2I2314ANZ also includes a serial
interface which can enable or disable each output clock.
On power-up, all output clocks are enabled. A separate
Output Enable pin facilitates testing on ATE.
*Pentium is a registered trademark of Intel Corporation.
Block Diagram
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDATA
Serial Interface
Decoding
SCLOCK
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
OE
SDRAM13
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
June 2005
rev 0.4
Pin Configuration
28- Pin SOIC Package -- Top View
V
DD
SDRAM0
SDRAM1
V
SS
V
DD
SDRAM2
SDRAM3
V
SS
BUF_IN
SDRAM4
SDRAM5
SDRAM12
V
DDIICC
SDATA
1
2
3
4
5
6
7
28
27
26
25
24
23
22
ASM22314ANZ
V
DD
SDRAM11
SDRAM10
V
SS
V
DD
SDRAM9
SDRAM8
V
SS
OE
SDRAM7
SDRAM6
SDRAM13
V
SSIIC
SCLK
ASM2I2314ANZ
8
9
10
11
12
13
14
21
20
19
18
17
16
15
Pin Description
Pins
1, 5, 24, 28
4, 8, 21, 25
13
16
9
20
14
15
2, 3, 6, 7, 10, 11, 18, 19,
22, 23, 26, 27, 12, 17
V
DD
V
SS
V
DDIIC
V
SSIIC
BUF_IN
OE
SDATA
SCLK
SDRAM [0-13]
Name
Type
P
P
P
P
I
I
I/O
I
O
Ground
Description
3.3V Digital voltage supply
3.3V Serial Interface Voltage supply
Ground for serial interface
Input clock .5V Tolerant
Output Enable, three-states outputs when LOW.
Internal pull-up to V
DD
Serial data input, internal pull-up to V
DD
.
5V Tolerant
Serial clock input, internal pull-up to V
DD.
5V Tolerant
SDRAM Clock Outputs
Device Functionality
OE
0
1
SDRAM [0-13]
High-Z
1 x BUF_IN
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
2 of 13
June 2005
rev 0.4
Serial Configuration Map
•
The Serial bits will be read by the clock driver in the
following order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
•
Reserved bits should be programmed to “0” or “1”.
•
Serial interface address for the ASM2I2314ANZ is:
ASM2I2314ANZ
Byte 1: SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
27
26
23
22
--
--
19
18
Description
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
Reserved
Reserved
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Byte 0:SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 2: SDRAM Active/Inactive Register
(1 = Enable, 0 = Disable), Default = Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
11
10
--
--
7
6
3
2
Description
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
Reserved
Reserved
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
Pin #
17
12
--
--
--
--
--
--
Description
SDRAM13 (Active/Inactive)
SDRAM12 (Active/Inactive)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value
of all the bits is high after chip is powered up.
IIC Byte Flow
Byte
1
2
3
4
5
6
Description
IIC Address
Command (dummy value, ignored)
Byte Count (dummy value, ignored)
IIC Data Byte 0
IIC Data Byte 1
IIC Data Byte 2
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
3 of 13
June 2005
rev 0.4
Absolute Maximum Ratings
Symbol
V
DD
V
IN
V
BUFIN
T
STG
T
J
T
DV
ASM2I2314ANZ
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except BUF_IN)
DC Input Voltage (BUF_IN)
Storage Temperature
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
Rating
–0.5 to +7.0
–0.5 to V
DD
+ 0.5
–0.5 to +7.0
–65 to +150
150
2
Unit
V
V
V
°
C
°
C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions
1
Parameter
V
DD
T
A
C
L
C
IN
t
PU
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Power-up time for all V
DD
's to reach minimum specified voltage
(power ramps must be monotonic)
Description
Min
3.135
0
-
-
0.05
Max
3.465
70
30
7
50
Unit
V
°C
pF
pF
mS
Note: 1. Electrical parameters are guaranteed under the operating conditions specified.
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
4 of 13
June 2005
rev 0.4
Electrical Characteristics
(Test condition: All parameters values are valid within the Operating range, unless otherwise stated)
ASM2I2314ANZ
Parameter
V
IL
V
ILIIC
V
IH
V
OL
V
OH
I
CC
I
OZ
I
OFF
∆I
CC
I
i
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
I
DDS
Description
Input LOW Voltage
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
1
1
Test Conditions
Except serial interface pins
For serial interface pins only
I
OL
= 25 mA
I
OH
= –36 mA
V
DD
= 3.465V, V
i
= V
DD
or GND, I
O
=0
V
DD
= 3.465V, V
i
= V
DD
or GND
V
DD
= 0V, V
i
= 0V or 5.5V
V
DD
= 3.135V to 3.465V
One Input at V
DD
-0.6, All other Inputs at
V
DD
or GND
V
DD
= 3.465V or GND
(Applicable to all Input Pins)
Unloaded outputs, 133 MHz
Loaded outputs, 30pF, 133 MHz
Unloaded outputs, 100 MHz
Loaded outputs, 30pF ,100 MHz
Unloaded outputs, 66.67 MHz
Loaded outputs, 30pF ,66.67 MHz
BUF_IN=V
DD
or V
SS
All other inputs at
V
DD
Min
-
-
2.0
-
2.4
Typ
Max
0.8
0.7
-
0.4
-
Unit
V
V
V
V
V
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
µA
Output HIGH Voltage
Quiescent Supply
Current
High Impedance
Output Current
Off-State Current
(for SCL ,SDATA)
Change in Supply
Current
Input Leakage
Supply Current
1
Supply Current
Supply Current
Supply Current
1
1
1
50
100
±10
50
500
-5
+5
266
360
-
-
-
-
-
200
290
150
185
500
Supply Current
1
Supply Current
1
Supply Current
Note: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production.
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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