Advance information
3.3V 2M
×
8/1M
×
16 CMOS synchronous DRAM
Features
• Organization
- 1,048,576 words × 8 bits × 2 banks (2M × 8)
11 row, 9 column address
- 524,288 words × 16 bits × 2 banks (1M × 16)
11 row,8 column address
AS4LC2M8S1
AS4LC1M16S1
• All signals referenced to positive edge of clock, fully
synchronous
• Dual internal banks controlled by A11 (bank select)
• High speed
- 143/125/100 MHz
- 7/8/10 ns clock access time
• PC100 functionality
• Automatic and direct precharge including concurrent
autoprecharge
• Burst read, write/Single write
• Random column address assertion in every cycle, pipelined
operation
• LVTTL compatible I/O
• 3.3V power supply
• JEDEC standard package, pinout and function
- 400 mil, 44-pin TSOP II (2M × 8)
- 400 mil, 50-pin TSOP II (1M × 16)
• Low power consumption
- Active: 576 mW max
- Standby: 7.2 mW max, CMOS I/O
• 2048 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh (2K self refresh mode at 64 ms)
• Read/write data masking
• Programmable burst length (1/2/4/8/ full page)
• Programmable burst sequence (sequential/interleaved)
• Programmable CAS latency (1/2/3)
Pin arrangement
TSOP II
V
CC
DQ0
V
SSQ
DQ1
V
CCQ
DQ2
V
SSQ
DQ3
V
CCQ
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
DQ7
V
SSQ
DQ6
V
CCQ
DQ5
V
SSQ
DQ4
V
CCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
CCQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
CCQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TSOP II
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
AS4LC1M16S0
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
CCQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
CCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
Pin designation
Pin(s)
DQM (2M × 8)
UDQM/LDQM (1M × 16)
A0 to A10
A11
DQ0 to DQ7 (2M
×
8)
DQ0 to DQ15 (1M
×
16)
RAS
CAS
WE
CS
V
CC
, V
CCQ
V
SS
, V
SSQ
CLK
CKE
Description
Output disable/write mask
RA0 – 10
Address inputs CA0 – 7 (
×
16)
CA0 – 8 (
×
8)
Bank address (BA)
Input/output
Row address strobe
Column address strobe
Write enable
Chip select
Power (3.3V ± 0.3V)
Ground
Clock input
Clock enable
AS4LC2M8S0
LEGEND
Configuration
Refresh Count
Row Address
Bank Address
Column Address
2M
×
8
1M
×
8
×
2 banks
2K
2K (A0 – A10)
2 (BA)
512 (A0 – A8)
1M
×
16
512K
×
16
×
2 banks
2K
2K (A0 – A10)
2 (BA)
256 (A0 – A7)
Selection guide
Symbol
Bus frequency (CL = 3)
Maximum clock access time (CL = 3)
Minimum input setup time
Minimum input hold time
Row cycle time (CL = 3, BL = 1)
Maximum operating current ([
×
16], RD or
WR, CL = 3), BL = 2
Maximum CMOS standby current, self refresh
7/5/00
–7
143
5.5
2
1.0
70
130
1
–8
125
6
2
1.0
80
100
1
–10
100
6
2
1.0
80
100
1
Unit
MHz
ns
ns
ns
ns
mA
mA
f
Max
t
AC
t
S
t
H
t
RC
I
CC1
I
CC6
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS4LC2M8S1
AS4LC1M16S1
Functional description
The AS4LC2M8S1 and AS4LC1M16S1 are high-performance 16-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM)
devices organized as 1,048,576 words × 8 bits × 2 banks (2048 rows × 512 columns) and 524,288 words × 16 bits × 2 banks
(2048 rows × 256 columns), respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are
referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data (512 bytes for
2M × 8 and 256 bytes for 1M × 16) without selecting a new column address.
The operational advantages of an SDRAM are as follows: (1) the ability to synchronously output data at a high clock frequency with
automatic increments of column-address (burst access); (2) bank-interleaving, which hides precharge time and attains seamless op eration;
and (3) the capability to change column-address randomly on every clock cycle during burst access.
This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type
(sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum
frequency of operation. This feature enables flexible performance optimization for a variety of applications.
SDRAM commands and functions are decoded from control inputs. Basic commands are as follows:
• Mode register set
• Select column; write
• Auto precharge with read/write
• Deactivate bank
• Select column; read
• Self-refresh
• Deactivate all banks
• Deselect; power down
• Select row; activate bank
• CBR refresh
Both devices are available in 400-mil plastic TSOP type 2 package. The AS4LC2M8S1 has 44 pins, and the AS4LC1M16S1 has 50 pins. Both
devices operate with a power supply of 3.3V ± 0.3V. Multiple power and ground pins are provided for low switching noise and EMI. Inputs
and outputs are LVTTL compatible.
Logic block diagram
CLK
Clock generator
CKE
A11
A[10:0]
Bank select
Row
address
buffer
Mode register
Refresh
counter
Row decoder
Bank A†
512K
×
16 (2048
×
256
×
16)
Bank B†
512K
×
16 (2048
×
256
×
16)
Sense amplifier
DQMU/DQML
Command decoder
CS
RAS
CAS
WE
Latch circuit
Column
address
buffer
Burst
counter
Input and output buffer
Control logic
Column decoder and
latch circuit
Data control circuit
DQ
† For AS4LC2M8S1, Banks A and B will read 1M × 8 (2048 × 512 × 8).
2
ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC2M8S1
AS4LC1M16S1
Pin descriptions
Pin
CLK
Name
System clock
Description
All operations synchronized to rising edge of CLK.
Controls CLK input. If CKE is high, the next CLK rising edge is valid.
If CKE is low, the internal clock is suspended from the next clock
cycle and the burst address and output states are frozen. If both banks
are idle and CKE goes low, the SDRAM will enter power down mode
from the next clock cycle. When in power down mode and CKE is
low, no input commands will be acknowledged. To exit power down
mode, raise CKE high before the rising edge of CLK.
Enables or disables device operation by masking or enabling all
inputs except CLK, CKE, UDQM/LDQM (×16), DQM (×8).
Row and column addresses are multiplexed. Row address: A0~A10.
Column address (2M × 8): A0~A8. Column address (1M × 16):
A0~A7.
Memory cell array is organized in 2 banks. A11 selects which internal
bank will be active. A11 is latched during bank activate, read, write,
mode register set, and precharge operations. Asserting A11 low
selects Bank A; A11 high selects Bank B.
Command inputs.
RAS, CAS, and WE, along with CS, define the command being
entered.
Controls I/O buffers. When DQM is high, output buffers are disabled
during a read operation and input data is masked during a write
operation. DQM latency is 2 clocks for Read and 0 clocks for Write.
For ×16, LDQM controls the lower byte (DQ0 – 7) and UDQM
controls the upper byte (DQ8 – 15). UDQM and LDQM are
considered to be in the same state when referred to jointly as DQM.
Data inputs/outputs are multiplexed.
Power and ground for core logic and input buffers.
Power and ground for data output buffers.
CKE
Clock enable
CS
A0~A10
Chip select
Address
A11
RAS
CAS
WE
Bank select
Row address strobe
Column address strobe
Write enable
×8: DQM
×16: UDQM, LDQM
Output disable/ write mask
DQ0~DQ15
V
CC
/V
SS
V
CCQ
/V
SSQ
Data input/output
Power supply/ground
Data output power/ground
7/5/00
ALLIANCE SEMICONDUCTOR
3
AS4LC2M8S1
AS4LC1M16S1
Operating modes
Command
Mode register set
Auto refresh
Entry
Self
refresh
Bank activate
Read
Write
Burst stop
Precharge
Selected bank
Both banks
Entry
Exit
Entry
Precharge power
down mode
Exit
DQM
No operation command
* V = Valid.
CKEn-1 CKEn
H
H
H
L
H
H
H
H
H
H
L
H
L
H
H
X
H
L
H
X
X
X
X
X
L
H
L
H
X
X
CS
L
L
L
L
H
L
L
L
L
L
H
L
X
H
L
H
L
X
H
L
RAS
L
L
L
H
X
L
H
H
H
L
X
V
X
X
H
X
H
X
X
H
CAS
L
L
L
H
X
H
L
L
H
H
X
V
X
X
H
X
H
X
X
H
WE
L
H
H
H
X
H
H
L
L
L
X
V
X
X
H
X
H
X
X
H
DQM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
A11
A10
Op code
X
X
X
X
A9–A0
Note
1,2
3
3
3
3
Exit
V
*
V
V
row address
L
H
L
H
X
L
H
X
column
address
column
address
4
4,5
4
4,5
6
X
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
V
X
Clock suspend or
active power down
X
X
X
X
X
7
1
2
3
4
5
6
7
OP= operation code.
A0~A11 see page 5.
MRS can be issued only when both banks are precharged and no data burst is ongoing. A new command can be issued 2 clock cycles a fter MRS.
Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic.
Auto/self refresh can only be issued after both banks are precharged.
A11: bank select address. If low during read, write, row active and precharge, bank A is selected.
If high during those states, bank B is selected. Both banks are selected and A11 is ignored if A10 is high during row precharge.
A new read/write/deac command to the same bank cannot be issued during a burst read/write with auto precharge.
A new row active command can be issued after t
RP
from the end of the burst.
Burst stop command valid at every burst length except full-page burst.
DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0).
Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).
4
ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC2M8S1
AS4LC1M16S1
Mode register fields
Address
Function
†
RFU = 0 during MRS cycle.
A11~A10
RFU
†
Register programmed with MRS
A9
A8
A7
A6
A5
A4
WBL
TM
CAS
latency
A3
BT
A2
A1
A0
Burst length
Write burst length
A9
Length
Programmed
0
burst length
1
Single burst
Burst type
A3
Type
0
Sequential
1
Interleaved
A8
0
0
1
1
Test mode
A7
Type
0 Mode register set
1
Reserved
0
Reserved
1
Reserved
CAS latency
A4
Latency
0
Reserved
1
1
0
2
1
3
X
Reserved
Burst length
A0
0
1
0
1
0
1
0
1
A6
0
0
0
0
1
A5
0
0
1
1
X
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
BT = 0
1
2
4
8
Reserved
Reserved
Reserved
Full page
BT = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Burst sequence (burst length = 4)
Initial address
A1
0
0
1
1
Initial address
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
2
3
Sequential
1
2
2
3
3
0
0
1
Interleave
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
Burst sequence (burst length = 8)
A2
0
0
0
0
1
1
1
1
A0
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
Sequential
3
4
4
5
5
6
6
7
7
0
0
1
1
2
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
Interleave
3
4
2
5
1
6
0
7
7
0
6
1
5
2
4
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
7/5/00
ALLIANCE SEMICONDUCTOR
5
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