August 2004
rev 2.0
3.3V Zero-Delay Buffer
General Features
•
Zero input - output propagation delay, adjustable by
capacitive load on FBK input.
•
Zero input - output propagation delay, adjustable by
capacitive load on FBK input.
•
Multiple configurations - Refer “ASM5P2308A
Configurations Table”.
•
•
Input frequency range: 10MHz to 133MHz
Multiple low-skew outputs.
•
•
•
Output-output skew less than 200 ps.
Device-device skew less than 700 ps.
Two banks of four outputs, three-stateable by two
The
ASM5P2308A
is
available
ASM5P2308A
which can be controlled by the select inputs as shown in
the Select Input Decoding Table. If all the output clocks are
not required, Bank B can be three-stated. The select input
also allows the input clock to be directly applied to the
outputs for chip and system testing purposes.
Multiple ASM5P2308A devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
700ps.
in
five
different
configurations (Refer “ASM5P2308A Configurations Table).
The ASM5P2308A-1 is the base part, where the output
frequencies equal the reference if there is no counter in the
feedback path. The ASM5P2308A-1H is the high-drive
version of the -1 and the rise and fall times on this device
are much faster.
select inputs.
•
•
•
•
•
Less than 200 ps cycle-to-cycle jitter (-1, -1H, -4, -5H).
Available in 16-pin SOIC and TSSOP packages.
3.3V operation.
Advanced 0.35µ CMOS technology.
Industrial temperature and pb free packages available.
Functional Description
ASM5P2308A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It is available in a
16-pin package. The part has an on-chip PLL which locks
to an input clock presented on the REF pin. The PLL
feedback is required to be driven to FBK pin, and can be
obtained from one of the outputs. The input-to-input
propagation delay is guaranteed to be less than 350ps, and
the output-to-output skew is guaranteed to be less than
250ps.
The ASM5P2308A-2 allows the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration
and output frequencies depends on which output drives the
feedback pin. The ASM5P2308A-3 allows the user to
obtain 4X and 2X frequencies on the outputs.
The ASM5P2308A-4 enables the user to obtain 2X clocks
on all outputs. Thus, the part is extremely versatile, and
can be used in a variety of applications.
The ASM5P2308A-5H is a high-drive version with REF/2
on both banks.
The ASM5P2308A has two banks of four outputs each,
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
August 2004
rev 2.0
Block Diagram
/2
REF
ASM5P2308A
ASM5P2308A
FBK
PLL
MUX
CLKA1
CLKA2
/2
Extra Divider (-3,-4)
Extra Divider (-5H)
S2
Select Input
Decoding
S1
/2
CLKA3
CLKA4
CLKB1
CLKB2
Extra Divider (-2,-3)
CLKB3
CLKB4
Select Input Decoding for ASM5P2308A
S2
0
0
1
1
S1
0
1
0
1
Clock A1 - A4
Three-state
Driven
Driven
1
Driven
Clock B1 - B4
Three-state
Three-state
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shut-Down
Y
N
Y
N
ASM5P2308A Configurations
Device
ASM5P2308A-1
ASM5P2308A-1H
ASM5P2308A-2
ASM5P2308A-2
ASM5P2308A-3
ASM5P2308A-3
ASM5P2308A-4
ASM5P2308A-5H
Note:
1. Outputs inverted on 2308-2 and 2308-3 in bypass mode, S2 = 1 and S1 = 0.
2. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the ASM5P2308A-2.
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference /2
Bank B Frequency
Reference
Reference
Reference /2
Reference
Reference or Reference
2
2 X Reference
2 X Reference
Reference /2
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
August 2004
rev 2.0
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between input and output.
ASM5P2308A
1500
1000
REF- Input to CLKA/CLKB Delay
500
0
-30
-500
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-1000
-1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
To close the feedback loop of the ASM5P2308A, the FBK pin can be driven from any of the eight available output pins. The
output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this
output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded.
If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback
output and remaining outputs. For zero output-output skew, be sure to load outputs equally.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
August 2004
rev 2.0
Pin Configuration
REF
CLKA1
CLKA2
V
DD
ASM5P2308A
1
2
3
4
5
6
7
8
16
15
14
13
FBK
CLKA4
CLKA3
V
DD
GND
CLKB1
CLKB2
S2
ASM5P2308A
12
11
10
9
GND
CLKB4
CLKB3
S1
Pin Description for ASM5P2308A
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Notes:
3. Weak pull-down.
4. Weak pull-down on all outputs.
5. Weak pull-up on these inputs.
Pin Name
REF
3
CLKA1
CLKA2
V
DD
GND
CLKB1
4
CLKB2
4
S2
5
S1
5
CLKB3
4
4
4
Description
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
Ground
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3V supply
Buffered clock output, bank A
Buffered clock output, bank A
PLL feedback input
CLKB4
4
GND
V
DD
CLKA3
4
CLKA4
4
FBK
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
August 2004
rev 2.0
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (per MIL-STD-883, Method 3015)
ratings for prolonged periods can affect device reliability.
Min
-0.5
-0.5
-0.5
-65
Max
+7.0
VDD + 0.5
7
+150
260
150
>2000
Unit
V
V
V
°C
°C
°C
V
ASM5P2308A
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum
Operating Conditions for ASM5P2308A Commercial Temperature Devices
Parameter
V
DD
T
A
C
L
C
L
C
IN
Note:
6. Applies to both Ref Clock and FBK.
Description
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
6
Min
3.0
0
Max
3.6
70
30
10
7
Unit
V
°C
pF
pF
pF
Electrical Characteristics for ASM5P2308A Commercial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
7
Output HIGH Voltage
7
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8mA (-1, -2, -3, -4)
I
OH
= 12mA (-1H, -5H)
I
OL
= -8mA (-1, -2, -3, -4)
I
OH
= -12mA (-1H, -5H)
Unloaded outputs 100MHz REF
I
DD
Supply Current
Select inputs at V
DD
or GND
Unloaded outputs, 66MHz REF (-1, -2, -3, -4)
Unloaded outputs, 33MHz REF (-1, -2, -3, -4)
TBD
TBD
TBD
TBD
mA
2.4
V
2.0
50.0
100.0
0.4
Test Conditions
Min
Max
0.8
Unit
V
V
µA
µA
V
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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