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5962H9654101VEC

产品描述J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, CERAMIC, DIP-16
产品类别逻辑    逻辑   
文件大小167KB,共19页
制造商Cobham PLC
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5962H9654101VEC概述

J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, CERAMIC, DIP-16

5962H9654101VEC规格参数

参数名称属性值
包装说明DIP, DIP16,.3
Reach Compliance Codeunknown
ECCN代码3A001.A.1.A
系列ACT
JESD-30 代码R-XDIP-T16
JESD-609代码e4
长度19.05 mm
负载电容(CL)50 pF
逻辑集成电路类型J-KBAR FLIP-FLOP
最大I(ol)0.008 A
位数2
功能数量2
端子数量16
最高工作温度125 °C
最低工作温度-55 °C
输出极性COMPLEMENTARY
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DIP
封装等效代码DIP16,.3
封装形状RECTANGULAR
封装形式IN-LINE
电源5 V
Prop。Delay @ Nom-Sup27 ns
传播延迟(tpd)27 ns
认证状态Qualified
筛选级别38535V;38534K;883S
座面最大高度5.08 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子面层GOLD
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
总剂量1M Rad(Si) V
触发器类型POSITIVE EDGE
宽度7.62 mm
最小 fmax62 MHz
Base Number Matches1

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REVISIONS
LTR
A
B
C
DESCRIPTION
Changes in accordance with NOR 5962-R144-97.
Incorporate Revision A. Update boilerplate to MIL-PRF-38535 requirements. –
LTG
Correct the title to accurately describe the device function. Change figure 4,
switching waveforms and test circuit. Update boilerplate to the latest
MIL-PRF-38535 requirements. - jak
Update radiation features in section 1.5 and SEP test limits in table IB. Correct
function of pin 10 in figure 1. Update boilerplate paragraphs as specified in
MIL-PRF-38535 requirements. - MAA
DATE (YR-MO-DA)
96-12-10
01-09-04
07-11-07
APPROVED
Monica L. Poelking
Thomas M. Hess
Thomas M Hess
D
11-04-19
David J. Corbett
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
D
15
D
16
D
17
D
18
REV
SHEET
PREPARED BY
Thanh V. Nguyen
CHECKED BY
Thanh V. Nguyen
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil/
APPROVED BY
Monica L. Poelking
DRAWING APPROVAL DATE
96-04-12
REVISION LEVEL
MICROCIRCUIT, DIGITAL, ADVANCED CMOS,
RADIATION HARDENED, DUAL J-K FLIP-FLOP
WITH CLEAR AND PRESET, TTL COMPATIBLE
INPUTS, MONOLITHIC SILICON
SIZE
CAGE CODE
AMSC N/A
D
A
67268
5962-96541
SHEET 1 OF 18
DSCC FORM 2233
APR 97
5962-E221-11

5962H9654101VEC相似产品对比

5962H9654101VEC 5962H9654101QXA 5962H9654101QXC 5962H9654101VXC 5962H9654101QEA 5962H9654101VXA 5962H9654101QEC 5962H9654101VEA
描述 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, CERAMIC, DIP-16 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM BRAZED, CERAMIC, DFP-16 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM BRAZED, CERAMIC, DFP-16 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM BRAZED, CERAMIC, DFP-16 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, CERAMIC, DIP-16 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, BOTTOM BRAZED, CERAMIC, DFP-16 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, CERAMIC, DIP-16 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDIP16, SIDE BRAZED, CERAMIC, DIP-16
包装说明 DIP, DIP16,.3 DFP, FL16,.3 DFP, FL16,.3 DFP, FL16,.3 DIP, DIP16,.3 DFP, FL16,.3 SIDE BRAZED, CERAMIC, DIP-16 SIDE BRAZED, CERAMIC, DIP-16
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown
ECCN代码 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A 3A001.A.1.A
系列 ACT ACT ACT ACT ACT ACT ACT ACT
JESD-30 代码 R-XDIP-T16 R-XDFP-F16 R-XDFP-F16 R-XDFP-F16 R-XDIP-T16 R-XDFP-F16 R-XDIP-T16 R-XDIP-T16
JESD-609代码 e4 e0 e4 e4 e0 e0 e4 e0
负载电容(CL) 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF
逻辑集成电路类型 J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP
最大I(ol) 0.008 A 0.008 A 0.008 A 0.008 A 0.008 A 0.008 A 0.008 A 0.008 A
位数 2 2 2 2 2 2 2 2
功能数量 2 2 2 2 2 2 2 2
端子数量 16 16 16 16 16 16 16 16
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C
输出极性 COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
封装主体材料 CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
封装代码 DIP DFP DFP DFP DIP DFP DIP DIP
封装等效代码 DIP16,.3 FL16,.3 FL16,.3 FL16,.3 DIP16,.3 FL16,.3 DIP16,.3 DIP16,.3
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 IN-LINE FLATPACK FLATPACK FLATPACK IN-LINE FLATPACK IN-LINE IN-LINE
电源 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
Prop。Delay @ Nom-Sup 27 ns 27 ns 27 ns 27 ns 27 ns 27 ns 27 ns 27 ns
传播延迟(tpd) 27 ns 27 ns 27 ns 27 ns 27 ns 27 ns 27 ns 27 ns
认证状态 Qualified Qualified Qualified Qualified Qualified Qualified Qualified Qualified
筛选级别 38535V;38534K;883S 38535Q/M;38534H;883B 38535Q/M;38534H;883B 38535V;38534K;883S 38535Q/M;38534H;883B 38535V;38534K;883S 38535Q/M;38534H;883B 38535V;38534K;883S
座面最大高度 5.08 mm 2.921 mm 2.921 mm 2.921 mm 5.08 mm 2.921 mm 5.08 mm 5.08 mm
最大供电电压 (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
表面贴装 NO YES YES YES NO YES NO NO
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY
端子面层 GOLD TIN LEAD GOLD GOLD TIN LEAD TIN LEAD GOLD TIN LEAD
端子形式 THROUGH-HOLE FLAT FLAT FLAT THROUGH-HOLE FLAT THROUGH-HOLE THROUGH-HOLE
端子节距 2.54 mm 1.27 mm 1.27 mm 1.27 mm 2.54 mm 1.27 mm 2.54 mm 2.54 mm
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
总剂量 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V 1M Rad(Si) V
触发器类型 POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
宽度 7.62 mm 6.731 mm 6.731 mm 6.731 mm 7.62 mm 6.731 mm 7.62 mm 7.62 mm
最小 fmax 62 MHz 62 MHz 62 MHz 62 MHz 62 MHz 62 MHz 62 MHz 62 MHz
Base Number Matches 1 1 1 1 1 1 1 1
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