Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope available in
TO220AB and SOT404 . Using
’trench’ technology which features
very low on-state resistance. It is
intended for use in automotive and
general
purpose
switching
applications.
BUK95150-55A
BUK96150-55A
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 5 V
V
GS
= 10 V
MAX.
55
13
53
175
150
137
UNIT
V
A
W
˚C
mΩ
mΩ
PINNING
TO220AB & SOT404
PIN
1
2
3
DESCRIPTION
gate
drain
2
PIN CONFIGURATION
mb
tab
SYMBOL
d
g
3
SOT404
1 2 3
source
1
tab/mb drain
TO220AB
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
±V
GSM
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
t
p
≤50µS
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
10
15
13
9
53
53
175
UNIT
V
V
V
V
A
A
A
W
˚C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient(TO220AB)
Thermal resistance junction to
ambient(SOT404)
CONDITIONS
-
in free air
Minimum footprint, FR4
board
TYP.
-
60
50
MAX.
2.8
-
-
UNIT
K/W
K/W
K/W
February 2000
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
DS
= 55 V; V
GS
= 0 V;
V
GS
=
±10
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 13 A
V
GS
= 10 V; I
D
= 13 A
V
GS
= 4.5 V; I
D
= 13 A
T
j
= 175˚C
T
j
= 175˚C
MIN.
55
50
1
0.5
-
-
-
-
-
-
-
-
BUK95150-55A
BUK96150-55A
TYP.
-
-
1.5
-
-
0.05
-
2
125
-
116
124
MAX.
-
-
2.0
-
2.3
10
500
100
150
300
137
161
UNIT
V
V
V
V
V
µA
µA
nA
mΩ
mΩ
mΩ
mΩ
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
L
d
L
d
L
d
L
s
PARAMETER
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal drain inductance
Internal source inductance
CONDITIONS
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
MIN.
-
-
-
-
-
-
-
-
-
-
-
TYP.
254
54
42
6
285
1
18
4.5
3.5
2.5
7.5
MAX.
339
65
58
6
428
1.4
25
-
-
-
-
UNIT
pF
pF
pF
ns
ns
ns
ns
nH
nH
nH
nH
V
DD
= 30 V; R
load
=1.2Ω;
V
GS
= 5 V; R
G
= 10
Ω
Measured from drain lead 6 mm
from package to centre of die
Measured from contact screw on
tab to centre of die(TO220AB)
Measured from upper edge of drain
tab to centre of die(SOT404)
Measured from source lead to
source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 53 A; V
GS
= 0 V
I
F
= 53 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 30 V
-
-
-
-
-
TYP.
-
-
0.85
1.1
24
0.026
MAX.
13
53
1.2
-
-
-
UNIT
A
A
V
V
ns
µC
February 2000
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS1
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 8 A; V
DD
≤
25 V;
V
GS
= 5 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
MIN.
-
BUK95150-55A
BUK96150-55A
TYP.
-
MAX.
25
UNIT
mJ
!
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
1000
ID/A
RDS(ON)=VSD/ID
100
1us
10us
tp=
10
DC
100us
1ms
10ms
1
0
20
40
60
80 100
Tmb / C
120
140
160
180
1
10
VSD/V
100
Fig.1. Normalised power dissipation.
PD% = 100⋅P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
10
Zth/(K/W)
0.5
0.2
1
0.1
0.05
0.02
0.1
0
0
20
40
60
80
100
Tmb / C
120
140
160
180
0.01
1E-07
1E-05
t/s
1E-03
1E-01
1E+01
Fig.2. Normalised continuous drain current.
ID% = 100⋅I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
1
For maximum permissible repetitive avalanche current see fig.18.
February 2000
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95150-55A
BUK96150-55A
100
ID/A 90
80
70
60
50
40
30
20
10
0
0
2
VGS/V =
10.0
7.5
7.0
6.5
6.0
5.5
5.0
4.8
4.4
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
70
ID/A
60
50
40
30
25 C
20
10
0
o
Tj/C= 175 C
o
4
VDS/V
6
8
10
0
1
2
3
VGS/V
4
5
6
7
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
RDS(ON)/mOhm
Fig.8. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
40
25
gfs/S
20
35
15
VGS/V=
30
3.0
3.2
3.4
3.6
4.0
5.0
10
25
5
0
20
0
0
10
20
30
5
10
15
ID/A
20
25
30
35
ID/A
40
50
60
70
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
RDS(ON)/mOhm
Fig.9. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Rds(on) normalised to 25degC
33
32
31
30
29
28
27
26
25
3
a
2.5
2
1.5
1
24
23
22
0.5
3
4
5
6
ID/A
7
8
9
10
-100
-50
0
50
100
Tmb / degC
150
200
Fig.7. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(V
GS
); conditions: I
D
= 13 A;
Fig.10. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 5 V
February 2000
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
BUK95150-55A
BUK96150-55A
2.5
VGS(TO) / V
max.
5
VGS / V
VDS = 14V
2
typ.
1.5
min.
1
4
VDS = 44V
3
2
0.5
1
0
-100
0
-50
0
50
Tj / C
100
150
200
0
5
10
QG / nC
15
20
Fig.11. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.14. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 25 A; parameter V
DS
1E-01
Sub-Threshold Conduction
100
90
IF/A
80
70
60
1E-02
2%
typ
98%
1E-03
Tj/C= 150 C
25 C
o
o
50
40
1E-04
30
20
1E-05
10
0
0.0
0.5
1.0
VSDS/V
1.5
2.0
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.12. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.15. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
WDSS%
Capacitance / nF
2.5
120
110
100
90
80
70
60
Ciss
2.0
1.5
1.0
50
40
30
0.5
Coss
Crss
20
10
0
20
40
60
80
100
120
Tmb / C
140
160
180
0.0
0.01
0.1
1
VDS/V
10
100
Fig.13. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.16. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 75 A
February 2000
5
Rev 1.000
微控制器 MCU
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