Schmitt input buffering, voltage translation, warm and cold spar-
ing. With V
DD
equal to zero volts, the UT54ACS162245S out-
puts and inputs present a minimum impedance of 1MΩ making
it ideal for "cold spare" applications. Balanced outputs and low
"on" output impedance make the UT54ACS162245S well suited
for driving high capacitance loads and low impedance back-
planes. The UT54ACS162245S enables system designers to in-
terface 2.5 volt CMOS compatible components with 3.3 volt
CMOS components. For voltage translation, the A port interfac-
es with the 2.5 volt bus; the B port interfaces with the 3.3 volt
bus. The direction control (DIRx) controls the direction of data
flow. The output enable (OEx) overrides the direction control
and disables both ports. These signals can be driven from either
port A or B. The direction and output enable controls operate
these devices as either two independent 8-bit transceivers or one
16-bit transceiver.
LOGIC SYMBOL
OE1 (48)
OE2 (25)
(1)
DIR1
(47)
(46)
(44)
G1
G2
2EN1 (BA)
2EN2 (AB)
1EN1 (BA)
1EN2 (AB)
11
12
(24)
DIR2
1A1
1A2
1A3
(2)
(3)
(5)
(6)
(8)
1B1
1B2
1B3
1B4
(43)
1A4
(41)
1A5
(40)
1A6
(38)
1A7
(37)
1A8
(36)
2A1
2A2
2A3
(35)
(33)
21
22
1B5
(9)
1B6
(11)
1B7
(12)
1B8
(13)
2B1
(14)
2B2
(16)
2B3
(17)
2B4
(19)
2B5
(20)
2B6
(22)
2B7
(23)
2B8
(32)
2A4
(30)
2A5
(29)
2A6
(27)
2A7
(26)
2A8
PIN DESCRIPTION
Pin Names
OEx
DIRx
xAx
xBx
Description
Output Enable Input (Active Low)
Direction Control Inputs
Side A Inputs or 3-State Outputs (2.5V Port)
Side B Inputs or 3-State Outputs (3.3V Port)
1
PINOUTS
When V
DD2
is at 2.5 volts, either 2.5 or 3.3 volts CMOS logic
levels can be applied to all control inputs. For proper operation
connect power to all V
DD
and ground all V
SS
pins (i.e., no float-
ing V
DD
or V
SS
input pins). Tie unused inputs to V
SS
. Always
insure V
DD1
> V
DD2
during operation of the part.
48-Lead Flatpack
Top View
FUNCTION TABLE
OE1
1A1
1A2
V
SS
1A3
1A4
VDD2
1A5
1A6
V
SS
1A7
1A8
2A1
2A2
V
SS
2A3
2A4
VDD2
2A5
2A6
V
SS
2A7
2A8
OE2
ENABLE
OEx
L
L
H
DIRECTION
DIRx
L
H
X
OPERATION
B Data To A Bus
A Data To B Bus
Isolation
DIR1
1B1
1B2
V
SS
1B3
1B4
VDD1
1B5
1B6
V
SS
1B7
1B8
2B1
2B2
V
SS
2B3
2B4
VDD1
2B5
2B6
V
SS
2B7
2B8
DIR2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
COLD/WARM SPARE FUNCTION
The device will place all outputs into a high-impedance state if
either V
DD
supply is taken to zero volts (I
WS
, warm spare), or
if both V
DD
supplies are set to zero volts (I
CS
, cold spare).
DEVICE POWER UP FUNCTION
The device will place all outputs into a high-impedance during
power-up. The high impedance state is maintained for a time
period approximately equal to the rise time of V
DD1
.
POWER TABLE
Port B
3.3 Volts
3.3 Volts
2.5 Volts
Port A
2.5 Volts
3.3 Volts
2.5 Volts
OPERATION
Voltage Translator
Non Translating
Non Translating
2
LOGIC DIAGRAM
DIR1
(1)
(48)
OE1
DIR2
(24)
(25)
OE2
1A1
(47)
(2)
1B1
2A1
(36)
(13)
2B1
1A2
(46)
(3)
1B2
2A2
(35)
(14)
2B2
1A3
(44)
(5)
1B3
2A3
(33)
(16)
2B3
3.3 V PORT
2.5V PORT
2.5V PORT
(6)
1A5
(41)
(8)
1A6
(40)
(9)
1A7
(38)
(11)
1A8
(37)
(12)
1B4
(17)
2A5
(30)
(19)
2A6
(29)
(20)
2A7
(27)
(22)
2A8
(26)
(23)
2B4
1B5
2B5
1B6
2B6
1B7
2B7
1B8
2B8
3
3.3 V PORT
1A4
(43)
2A4
(32)
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEL Latchup
Neutron Fluence
(Note 2)
LIMIT
1.0E5
>113
1.0E14
UNITS
rad(Si)
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent to CMOS technology.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
I/O (Note 2)
V
DD1
V
DD2
T
STG
T
J (Note 3)
Θ
JC
I
I
P
D
PARAMETER
Voltage any pin
Supply voltage
Supply voltage
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT (Mil only)
-.3 to V
DD1
+.3
-0.3 to 4.0
-0.3 to 4.0
-65 to +150
+150
20
±10
1
UNITS
V
V
V
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
2. For Cold Spare mode (V
DD1
=VSS, V
DD2
=VSS), V
I/O
may be -0.3V to the maximum recommended operating level of V
DD1
+0.3V.
3. Maximum junction temperature may be increased to +175
NAND ID is 0xecf1
Memory Test(30200000h-33ff0000h):O.K.
Load Wince Kernel...
run 0x3022bee0...
Windows CE Kernel for ARM (Thumb Enabled) Built on Jun 24 2004 at 18:25:00
Proc ......
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