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5962G9656101QCC

产品描述Binary Counter, ACT Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, CDIP16, SIDE-BRAZED, CERAMIC, DIP-16
产品类别逻辑    逻辑   
文件大小261KB,共11页
制造商Cobham PLC
下载文档 详细参数 全文预览

5962G9656101QCC概述

Binary Counter, ACT Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, CDIP16, SIDE-BRAZED, CERAMIC, DIP-16

5962G9656101QCC规格参数

参数名称属性值
包装说明DIP,
Reach Compliance Codeunknown
计数方向BIDIRECTIONAL
系列ACT
JESD-30 代码R-CDIP-T16
JESD-609代码e4
负载/预设输入YES
逻辑集成电路类型BINARY COUNTER
工作模式SYNCHRONOUS
位数4
功能数量1
端子数量16
最高工作温度125 °C
最低工作温度-55 °C
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DIP
封装形状RECTANGULAR
封装形式IN-LINE
传播延迟(tpd)24 ns
认证状态Not Qualified
筛选级别MIL-PRF-38535 Class Q
座面最大高度5.08 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子面层GOLD
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
总剂量500k Rad(Si) V
触发器类型POSITIVE EDGE
宽度7.62 mm
最小 fmax71 MHz
Base Number Matches1

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Standard Products
UT54ACS169/UT54ACTS169
4-Bit Up-Down Binary Counters
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Fully synchronous operation for counting and programming
Internal look-ahead for fast counting
Carry output for n-bit cascading
Fully independent clock circuit
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS169 - SMD 5962-96560
UT54ACTS169 - SMD 5962-96561
DESCRIPTION
The UT54ACS169 and the UT54ACTS169 are synchronous 4-
bit binary counters that feature an internal carry look-ahead for
cascading in high-speed counting applications. Synchronous
operation is provided by having all flip-flops clocked simulta-
neously so that the outputs change coincident with each other
when instructed by the count-enable inputs and internal gating.
Synchronous operation helps eliminate the output counting
spikes that are normally associated with asynchronous (ripple
clock) counters. The clock input triggers the four flip-flops on
the rising (positive-going) edge of the clock.
The counters are fully programmable (i.e., the outputs may each
be preset high or low). The load input circuitry allows loading
with the carry-enable output of cascaded counters. Loading is
synchronous; applying a low level at the load input disables the
counter and causes the outputs to agree with the data inputs after
the next clock pulse.
The carry look-ahead circuitry provides for cascaded counters
for n-bit synchronous application without additional gating. In-
strumental in accomplishing this function are two count-enable
inputs and a carry output. Assert both count enable inputs (ENP
and ENT) to count. The direction of the count is determined by
the level of the U/D input. When U/D is high, the counter counts
up; when low, it counts down. Input ENT is fed forward to
enable the carry output. The ripple carry output
RCO enables a low-level pulse while the count is zero (all inputs
low) counting down or maximum (15) counting up. The low-
level overflow carry pulse can be used to enable successive cas-
caded stages.
PINOUTS
16-Pin DIP
Top View
U/D
CLK
A
B
C
D
ENP
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
16-Lead Flatpack
Top View
U/D
CLK
A
B
C
D
ENP
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
Transitions at ENP or ENT are allowed regardless of the level
of the clock input.
The counters feature a fully independent clock circuit. Changes
at control inputs (ENP, ENT, LOAD, U/D) that modify the op-
erating mode have no effect on the contents of the counter until
clocking occurs. The function of the counter (whether enabled,
disabled, loading, or counting) will be dictated solely by the
conditions meeting the stable setup and hold times.
The devices are characterized over full military temperature
range of -55°C to +125°C.
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