UC1526A
UC2526A
UC3526A
Regulating Pulse Width Modulator
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Reduced Supply Current
Oscillator Frequency to 600kHz
Precision Band-Gap Reference
7 to 35V Operation
Dual 200mA Source/Sink Outputs
Minimum Output Cross-Conduction
Double-Pulse Suppression Logic
Under-Voltage Lockout
Programmable Soft-Start
Thermal Shutdown
TTL/CMOS Compatible Logic Ports
5 Volt Operation (V
IN
= V
C
= V
REF
= 5.0V)
DESCRIPTION
The UC1526A Series are improved-performance pulse-width modu-
lator circuits intended for direct replacement of equivalent non- “A”
versions in all applications. Higher frequency operation has been
enhanced by several significant improvements including: a more ac-
curate oscillator with less minimum dead time, reduced circuit de-
lays (particularly in current limiting), and an improved output stage
with negligible cross-conduction current. Additional improvements
include the incorporation of a precision, band-gap reference gener-
ator, reduced overall supply current, and the addition of thermal
shutdown protection.
Along with these improvements, the UC1526A Series retains the
protective features of under-voltage lockout, soft-start, digital cur-
rent limiting, double pulse suppression logic, and adjustable
deadtime. For ease of interfacing, all digital control ports are TTL
compatible with active low logic.
Five volt (5V) operation is possible for “logic level” applications by
connecting V
IN,
V
C
and V
REF
to a precision 5V input supply. Consult
factory for additional information.
BLOCK DIAGRAM
6/93
UC1526A
UC2526A
UC3526A
ABSOLUTE MAXIMUM RATINGS
(Note 1, 2)
Input Voltage (+V
IN)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V
Collector Supply Voltage (+V
C
) . . . . . . . . . . . . . . . . . . . . . +40V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +V
IN
Source/Sink Load Current (each output) . . . . . . . . . . . . 200mA
Reference Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Logic Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
Power Dissipation at T
A
= +25°C (Note 2) . . . . . . . . . 1000mW
Power Dissipation at T
C
= +25°C (Note 2) . . . . . . . . . . 3000mW
Operating Junction Temperature . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (soldering, 10 seconds) . . . . . . . . . . +300°C
RECOMMENDED OPERATING CONDITIONS
(Note 3)
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V to +35V
Collector Supply Voltage . . . . . . . . . . . . . . . . . . +4.5V to +35V
Sink/Source Load Current (each output) . . . . . . . . 0 to 100mA
Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA
Oscillator Frequency Range . . . . . . . . . . . . . . . . 1Hz to 600kHz
Oscillator Timing Resistor. . . . . . . . . . . . . . . . . . . 2kΩ to 150kΩ
Oscillator Timing Capacitor. . . . . . . . . . . . . . . . . 400pF to 20µF
Available Deadtime Range at 40kHz . . . . . . . . . . . . 1% to 50%
Operating Ambient Temperature Range
UC1526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
UC2526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
UC3526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Note 3: Range over which the device is functional and
parameter limits are guaranteed.
Note 1: Values beyond which damage may occur.
Note 2: Consult packaging Section of Databook for thermal
limitations and considerations of package.
CONNECTION DIAGRAMS
DIL-18, SOIC-18 (TOP VIEW)
J or N Package, DW Package
PLCC-20, LCC-20
(TOP VIEW)
Q and L Packages
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
+ERROR
-ERROR
COMP.
C
SS
RESET
- CURRENT SENSE
+ CURRENT SENSE
SHUTDOWN
R
TIMING
C
T
R
D
SYNC
OUTPUT A
V
C
N/C
GROUND
OUTPUT B
+V
IN
V
REF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2
UC1526A
UC2526A
UC3526A
ELECTRICAL CHARACTERISTICS:
+V
IN
= 15V, and over operating ambient temperature, unless otherwise specified T
A
= T
J.
UC1526A / UC2526A
PARAMETER
Reference Section (Note 4)
Output Voltage
Line Regulation
Load Regulation
Temperature Stability
Total Output Voltage
Range
Short Circuit Current
Under-Voltage Lockout
RESET Output Voltage
Oscillator Section (Note 6)
Initial Accuracy
Voltage Stability
Temperature Stability
Minimum Frequency
Maximum Frequency
Sawtooth Peak Voltage
Sawtooth Valley Voltage
SYNC Pulse Width
Input Offset Voltage
Input Bias Current
Input Offset Current
DC Open Loop Gain
HIGH Output Voltage
LOW Output Voltage
Common Mode Rejection
Supply Voltage Rejection
PWM Comparator (Note 6)
Minimum Duty Cycle
Maximum Duty Cycle
HIGH Output Voltage
LOW Output Voltage
HIGH Input Current
LOW Input Current
Shutdown Delay
Sense Voltage
Input Bias Current
Shutdown Delay
From pin 7, 100mV Overdrive, T
J
= 25°C
V
COMPENSATION
= +0.4V
V
COMPENSATION
= +3.6V
I
SOURCE
= 40µA
I
SINK
= 3.6mA
V
IH
= +2.4V
V
IL
= +0.4V
From Pin 8, T
J
= 25°C
R
S
≤
50Ω
90
45
2.4
49
4.0
0.2
-125
-225
160
100
-3
260
110
-10
80
0.4
-200
-360
0
45
2.4
49
4.0
0.2
-125
-225
160
100
-3
260
120
-10
0.4
-200
-360
0
%
%
V
V
µA
µA
ns
mV
µA
ns
R
L
≥
10MΩ
V
PIN 1
- V
PIN 2
≥
150mV, I
SOURCE
= 100µA
V
PIN 2
- V
PIN 1
≥
150mV, I
SINK
= 100µA
R
S
≤
2kΩ
+V
IN
= 12 to 18V
70
66
64
3.6
T
J
= +25°C
+V
IN
= 7 to 35V
Over Operating T
J
(Note 5)
R
T
= 150kΩ, C
T
= 20µF (Note 5)
R
T
= 2kΩ, C
T
= 470pF
+V
IN
= 35V
+V
IN
=7V
T
J =
25°C, R
L
= 2.7kΩ to V
REF
R
S
≤
2kΩ
0.5
550
3.0
1.0
1.1
2
-350
35
72
4.2
0.2
94
80
0.4
70
66
5
-1000
100
60
3.6
3.5
0.5
±3
0.5
2
±8
1
6
1
650
3.0
1.0
1.1
2
-350
35
72
4.2
0.2
94
80
0.4
10
-2000
200
3.5
±3
0.5
1
±8
1
3
1
%
%
%
Hz
kHz
V
V
µs
mV
nA
nA
dB
V
V
dB
dB
V
REF
= 3.8V
V
REF
= 4.7V
2.4
0.2
4.7
0.4
2.4
0.2
4.8
0.4
V
V
T
J
= +25°C
+V
IN
= 7 to 35V
I
L
= 0 to 20mA
Over Operating T
J
(Note 5)
Over Recommended Operating
Conditions
V
REF
= 0V
4.90
25
4.95
5.00
2
5
15
5.00
50
5.05
10
20
50
5.10
100
4.85
25
4.90
5.00
2
5
15
5.00
50
5.10
15
20
50
5.15
100
V
mV
mV
mV
V
mA
TEST CONDITIONS
MIN
TYP
MAX
MIN
UC3526A
TYP
MAX
UNITS
Error Amplifier Section (Note 7)
Digital Ports (SYNC, SHUTDOWN, and RESET)
Current Limit Comparator (Note 8)
Note 4: I
L =
0mA.
Note 5: Guaranteed by design, not 100% tested in production.
Note 6: F
OSC
= 40kHz, (R
T
= 4.12k
Ω ±
1%, C
T
= 0.01
µ
F
±
1%,
R
D
= 0
Ω
).
Note 7: V
CM
= 0 to +5.2V
Note 8: V
CM
= 0 to +12V.
Note 9: V
C
= +15V.
Note 10:V
IN
= +35V, R
T
= 4.12k
Ω
.
3
UC1526A
UC2526A
UC3526A
ELECTRICAL CHARACTERISTICS:
+V
IN
= 15V, and over operating ambient temperature, unless otherwise specified T
A
= T
J.
PARAMETER
Soft-Start Section
Error Clamp Voltage
C
S
Charging Current
HIGH Output Voltage
LOW Output Voltage
Collector Leakage
Rise Time
Fall Time
RESET = +0.4V
RESET = +2.4V
I
SOURCE
= 20mA
I
SOURCE
= 100mA
I
SINK
= 20mA
I
SINK
= 100mA
V
C
= 40V
C
L
= 1000pF (Note 5)
C
L
= 1000pF (Note 5)
50
12.5
12
0.1
100
13.5
13
0.2
1.2
50
0.3
0.1
8
14
20
0.3
2.0
150
0.6
0.2
0.4
150
50
12.5
12
0.1
100
13.5
13
0.2
1.2
50
0.3
0.1
8
14
20
0.3
2.0
150
0.6
0.2
0.4
150
V
µA
V
V
V
V
µA
µs
µs
nC
mA
TEST CONDITIONS
MIN
UC1526A
UC2526A
TYP
MAX
MIN
UC3526A
UNITS
TYP
MAX
Output Drivers (Each Output) (Note 9)
Cross-Conduction Charge Per cycle, T
J
= 25°C
Power Consumption (Note 10)
Standby Current
SHUTDOWN = +0.4V
Note 4: I
L =
0mA.
Note 5: Guaranteed by design, not 100% tested in production.
Note 6: F
OSC
= 40kHz, (R
T
= 4.12k
Ω ±
1%, C
T
= 0.01
µ
F
±
1%,
R
D
= 0
Ω
).
Note 7: V
CM
= 0 to +5.2V
Note 8: V
CM
= 0 to +12V.
Note 9: V
C
= +15V.
Note 10:V
IN
= +35V, R
T
= 4.12k
Ω
.
Open Loop Test Circuit UC1526A
4
UC1526A
UC2526A
UC3526A
APPLICATIONS INFORMATION
Voltage Reference
The reference regulator of the UC1526A is based on a
precision band-gap reference, internally trimmed to
±1%
accuracy. The circuitry is fully active at supply voltages
above +7V, and provides up to 20mA of load current to
external circuitry at +5.0V. In systems where additional
current is required, an external PNP transistor can be
used to boost the available current. A rugged low fre-
quency audio-type transistor should be used, and lead
lengths between the PWM and transistor should be as
short as possible to minimize the risk of oscillations.
Even so, some types of transistors may require collec-
tor-base capacitance for stability. Up to 1 amp of load
current can be obtained with excellent regulation if the
device selected maintains high current gain.
Figure 2.
Under-Voltage Lockout Schematic
Soft-Start Circuit
The soft-start circuit protects the power transistors and
rectifier diodes from high current surges during power
supply turn-on. When supply voltage is first applied to
the UC1526A, the under-voltage lockout circuit holds
RESET LOW with Q
3
. Q
1
is turned on, which holds the
soft-start capacitor voltage at zero. The second collector
of Q
1
clamps the output of the error amplifier to ground,
guaranteeing zero duty cycle at the driver outputs.
When the supply voltage reaches normal operating
range, RESET will go HIGH. Q
1
turns off, allowing the
internal 100µA current source to charge C
S
. Q
2
clamps
the error amplifier output to 1V
BE
above the voltage on
C
S
. As the soft-start voltage ramps up to +5V, the duty
cycle of the PWM linearly increases to whatever value
the voltage regulation loop requires for an error null.
Figure 1.
Extending Reference Output Current
Under-Voltage Lockout
The under-voltage lockout circuit protects the UC1526A
and the power devices it controls from inadequate sup-
ply voltage, If +V
IN
is too low, the circuit disables the
output drivers and holds the RESET pin LOW. This pre-
vents spurious output pulses while the control circuitry is
stabilizing, and holds the soft-start timing capacitor in a
discharged state.
The circuit consists of a +1.2V bandgap reference and
comparator circuit which is active when the reference
voltage has risen to 3V
BE
or +1.8V at 25°C. When the
reference voltage rises to approximately +4.4V, the cir-
cuit enables the output drivers and releases the RESET
pin, allowing a normal soft-start. The comparator has
350mV of hysteresis to minimize oscillation at the trip
point. When +V
IN
to the PWM is removed and the refer-
ence drops to +4.2V, the under-voltage circuit pulls RE-
SET LOW again. The soft-start capacitor is immediately
discharged, and the PWM is ready for another soft-start
cycle.
The UC1526A can operate from a +5V supply by con-
necting the V
REF
pin to the +V
IN
pin and maintaining the
supply between +4.8 and +5.2V.
Figure 3.
Soft-Start Circuit Schematic
Digital Control Ports
The three digital control ports of the UC1526A are bi-di-
rectional. Each pin can drive TTL and 5V CMOS logic di-
rectly, up to a fan-out of 10 low-power Schottky gates.
Each pin can also be directly driven by open-collector
TTL, open-drain CMOS, and open-collector voltage
comparators; fan-in is equivalent to 1 low-power Schot-
tky gate. Each port is normally HIGH; the pin is pulled
LOW to activate the particular function. Driving SYNC
LOW initiates a discharge cycle in the oscillator. Pulling
SHUTDOWN LOW immediately inhibits all PWM output
pulses. Holding RESET LOW discharges the soft-start
5
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