HB52D328DC-B
256 MB Unbuffered SDRAM S.O.DIMM
32-Mword
×
64-bit, 100 MHz Memory Bus, 2-Bank Module
(8 pcs of 16 M
×
16 components)
PC100 SDRAM
E0084H10 (1st edition)
(Previous ADE-203-1188A (Z))
Jan. 31, 2001
Description
The HB52D328DC is a 16M
×
64
×
2 banks Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 8 pieces of 256-Mbit SDRAM (HM5225165BTT) sealed in TSOP
package and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the product is 144-
pin Zig Zag Dual tabs socket type compact and thin package. Therefore, it makes high density mounting
possible without surface mount technology. It provides common data inputs and outputs. Decoupling
capacitors are mounted beside TSOP on the module board.
Features
•
Fully compatible with : JEDEC standard outline 8-byte S.O.DIMM
: Intel PCB Reference design (Rev.1.0)
•
144-pin Zig Zag Dual tabs socket type (dual lead out)
Outline: 67.60 mm (Length)
×
31.75 mm (Height)
×
3.80 mm (Thickness)
Lead pitch: 0.80 mm
•
3.3 V power supply
•
Clock frequency: 100 MHz (max)
•
LVTTL interface
•
Data bus width:
×
64 Non parity
•
Single pulsed
RAS
•
4 Banks can operates simultaneously and independently
•
Burst read/write operation and burst read/single write operation capability
•
Programmable burst length : 1/2/4/8
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB52D328DC-B
•
2 variations of burst sequence
Sequential (BL = 1/2/4/8)
interleave (BL = 1/2/4/8)
•
Programmable
CE
latency : 2/3 (HB52D328DC-A6B/A6BL)
: 3 (HB52D328DC-B6B/B6BL)
•
Byte control by DQMB
•
Refresh cycles: 8192 refresh cycles/64 ms
•
2 variations of refresh
Auto refresh
Self refresh
•
Low self refresh current: HB52D328DC-A6BL/B6BL (L-version)
Ordering Information
Type No.
HB52D328DC-A6B
HB52D328DC-B6B
HB52D328DC-A6BL
HB52D328DC-B6BL
Frequency
100 MHz
100 MHz
100 MHz
100 MHz
CE
latency
2/3
3
2/3
3
Package
Small outline DIMM (144-pin)
Contact pad
Gold
Data Sheet E0084H10
2
HB52D328DC-B
Pin Description
Pin name
A0 to A12
Function
Address input
Row address
Column address
BA0/BA1
DQ0 to DQ63
S0/S1
RE
CE
W
DQMB0 to DQMB7
CK0/CK1
CKE0/CKE1
SDA
SCL
V
CC
V
SS
NC
Bank select address
Data-input/output
Chip select
Row address asserted bank enable
Column address asserted
Write enable
Byte input/output mask
Clock input
Clock enable
Data-input/output for serial PD
Clock input for serial PD
Power supply
Ground
No connection
A0 to A12
A0 to A8
Data Sheet E0084H10
5
TI技术论坛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
