DATASHEET
CLOCK DISTRIBUTION CIRCUIT
Description
The IDT6T39007A is a low-power, four output clock
distribution circuit. The device takes a TCXO or 1.8 V to
2.5 V LVCMOS input and generates four high-quality LVDS
outputs, and two programmable divided outputs.
It includes a redundant input with automatic glitch-free
switching when the primary reference is removed. The
primary input may be selected by the user by pulling the
SEL pin low or high. If the primary input is removed and
brought back, it will not be re-selected until 1024 cycles
have passed.
The IDT6T39007A specifically addresses the needs of
handheld applications in both performance and package
size. The device is packaged in a small 4mm x 4mm 24-pin
QFN, allowing optimal use for limited board space.
IDT6T39007A
Features
•
•
•
•
•
Packaged in 24-pin QFN
TCXO sine wave input
+2.5 V operating voltage
Four buffered LVDS outputs
Two programmable outputs for power control up to 3.0 V
LVCMOS levels based on VDDO1/VDDO2
•
Individual output enables controlled via I
2
C or OEx
•
Pb-free, RoHS compliant package
•
Industrial temperature range (-40°C to +85°C)
Block Diagram
VDD 2.5 V
3
SEL
SCLK
SDATA
LVCMOS_INB
OE1
OUT1 LVDS
OE2
OUT2 LVDS
OUT3 LVDS
OUT4 LVDS
TCXO_INA
±100mVpp
MUX
Divide
Logic
VDDO1
PWRCTRL_CLK1
VDDO2
PWRCTRL_CLK2
2
GND
IDT®
CLOCK DISTRIBUTION CIRCUIT
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IDT6T39007A REV H 022212
IDT6T39007A
CLOCK DISTRIBUTION CIRCUIT
DISTRIBUTION CIRCUITS
Pin Assignment
TCXO_INA
SEL
LVCMOS_INB
SEL Pin Configuration Table
SEL
0
GND
VDD
Primary Input
LVCMOS_INB
TCXO_INA
VDDO1
1
OE Pin Configuration Table
PWRCTRL_CLK1
PWRCTRL_CLK2
SCLK
SDATA
VDDO2
VDD
1
Thermal pad
connected to silicon
substrate.
Connect to ground
plane.
19
OUT1
OUT1B
OUT2
OUT2B
OUT3
OEx
0
1
OUTx LVDS
Disabled
Enabled
13
7
OUT3B
OUT4
GND
VDD
OUT4B
24- pin QFN
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin
Name
PWRCTRL_CLK1
PWRCTRL_CLK2
SCLK
SDATA
VDDO2
VDD
GND
VDD
OUT4B
OUT4
Pin
Type
Output
Output
Input
Input
Power
Power
Power
Power
Output
Output
OE2
OE1
Pin Description
Programmable power control output 1. See I
2
C table.
Programmable power control output 2. See I
2
C table.
I
2
C clock input.
I
2
C data input.
Connect to +3.0 V.
Connect to +2.5 V.
Connect to ground.
Connect to +2.5 V.
Buffered LVDS output. Outputs tri-state when disabled.
Buffered LVDS output. Outputs tri-state when disabled.
Output enable control for OUT2 LVDSpins. Internal pull-up resistor. See table above.
Output enable control for OUT1 LVDSpins. Internal pull-up resistor. See table above.
Buffered LVDS output. Outputs tri-state when disabled.
Buffered LVDS output. Outputs tri-state when disabled.
Buffered LVDS output. Outputs tri-state when disabled.
OE2
OE1
OUT3B
OUT3
OUT2B
Input
Input
Output
Output
Output
IDT®
CLOCK DISTRIBUTION CIRCUIT
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IDT6T39007A REV H 022212
IDT6T39007A
CLOCK DISTRIBUTION CIRCUIT
DISTRIBUTION CIRCUITS
Pin
Number
16
17
18
Pin
Name
OUT2
OUT1B
OUT1
GND
VDD
LVCMOS_INB
SEL
TCXO_INA
VDDO1
Pin
Type
Output
Output
Output
Power
Power
Input
Input
Input
Power
Pin Description
Buffered LVDS output. Outputs tri-state when disabled.
Buffered LVDS output. Outputs tri-state when disabled.
Buffered LVDS output. Outputs tri-state when disabled.
Connect to ground.
Connect to +2.5 V.
Connect to primary LVCMOS input INB. See table above.
Select pin for primary inputs. See table above. Internal pull-up resistor.
Connect to TCXO input.
Connect to +3.0 V.
19
20
21
22
23
24
IDT®
CLOCK DISTRIBUTION CIRCUIT
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IDT6T39007A REV H 022212
IDT6T39007A
CLOCK DISTRIBUTION CIRCUIT
DISTRIBUTION CIRCUITS
General I
2
C Serial Interface
How to Write:
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address D4
(H)
IDT clock will
acknowledge
Controller (host) sends the beginning byte location =N
IDT clock will
acknowledge
Controller (host) sends the data byte count = X
IDT clock will
acknowledge
Controller (host) starts sending
Byte N through Byte N + X - 1
(see Note 2)
IDT clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address D4
(H)
IDT clock will
acknowledge
Controller (host) sends the beginning byte location =N
IDT clock will
acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address D5
(H)
IDT clock will
acknowledge
Controller (host) sends the data byte count = X
IDT clock sends
Byte N + X - 1
IDT clock sends
Byte 0 through byte X (if X
(H)
was written to
byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
T
WR
starTbit
WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte = N
O
O
O
Byte N + X - 1
ACK
P
stoP bit
.
X
B
Y
T
E
ACK
ACK
O
O
O
O
O
O
N
P
ACK
.
X
B
Y
T
E
Beginning Byte N
O
O
O
Byte N + X - 1
Data Byte Count = X
RT
RD
Slave Address D4
(H)
Beginning Byte = N
ACK
IDT (Slave/Receiver)
Controller (Host)
T
WR
starTbit
Slave Address D4
(H)
WRite
ACK
IDT (Slave/Receiver)
Repeat starT
ReaD
ACK
Slave Address D5
(H)
Not acknowledge
stoP bit
IDT®
CLOCK DISTRIBUTION CIRCUIT
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IDT6T39007A REV H 022212
IDT6T39007A
CLOCK DISTRIBUTION CIRCUIT
DISTRIBUTION CIRCUITS
I
2
C Address
The IDT6T39007A is a slave-only device that supports block read and block write protocol using a single 7 bit address and
read/write bit. A block write (D4
(H)
) or block read (D5
(H)
) is made up of seven (7) bits and one (1) read/write bit.
A6
1
A5
1
A4
0
A3
1
A2
0
A1
1
A0
0
R/W#
X
In applications where the indexed block write and block read
are used, the dummy byte (bit 11-18) functions as a
register-offset (8 bits) pointer.
Byte 0: Control Register
Bit
7
6
5
4
3
2
1
0
Description
Reserved
Reserved
OE for OUT3
OE for OUT4
Reserved
Reserved
Reserved
Reserved
Type
R
R
RW
RW
R
R
R
R
Power Up
Condition
Undefined
Undefined
1
1
Undefined
Undefined
Undefined
Undefined
Output(s) Affected
Not applicable
Not applicable
Notes
LVDS clock output
LVDS clock output
Not applicable
Not applicable
Not applicable
Not applicable
1=enabled
0=disabled
1=enabled
0=disabled
IDT®
CLOCK DISTRIBUTION CIRCUIT
5
IDT6T39007A REV H 022212
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