CapSense Applications
Features
■
■
CY8C20X36/46/66/96
®
1.71V to 5.5V Operating Range
Low Power CapSense
®
Block
❐
Configurable Capacitive Sensing Elements
❐
Supports Combination of CapSense Buttons, Sliders,
Touchpads, Touch Screens, and Proximity Sensor
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds Running to 24 MHz
❐
Low Power at High Speed
❐
Interrupt Controller
❐
Temperature Range: -40°C to +85°C
Flexible On-Chip Memory
❐
Three Program/Data Storage Size Options:
• CY8C20x36: 8K Flash / 1K SRAM
• CY8C20x46, CY8C20x96: 16K Flash / 2K SRAM
• CY8C20x66: 32K Flash / 2K SRAM
❐
50,000 Flash Erase/Write Cycles
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
In-System Serial Programming (ISSP)
Full Speed USB
❐
Available on CY8C20646, CY8C20666, CY8C20x96 Only
❐
12 Mbps USB 2.0 Compliant
❐
Eight Unidirectional Endpoints
❐
One Bidirectional Control Endpoint
❐
Dedicated 512 Byte Buffer
❐
Internally Regulated at 3.3V
Precision, Programmable Clocking
❐
Internal Main Oscillator: 6/12/24 MHz ± 5%
❐
Internal Low Speed Oscillator at 32 kHz for Watchdog and
Sleep Timers
❐
Precision 32 kHz Oscillator for Optional External Crystal
❐
0.25% Accuracy for USB with No External Components
(CY8C20646, CY8C20666, CY8C20x96 only)
Programmable Pin Configurations
❐
Up to 36 GPIO (Depending on Package)
❐
Dual Mode GPIO: All GPIO Support Digital I/O and Analog
Input
❐
25 mA Sink Current on All GPIO
❐
Pull up, High Z, Open Drain Modes on All GPIO
❐
CMOS Drive Mode (5 mA Source Current) on Ports 0 and 1:
• 20 mA (at 3.0V) Total Source Current on Port 0
• 20 mA (at 3.0V) Total Source Current on Port 1
❐
Selectable, Regulated Digital I/O on Port 1
❐
Configurable Input Threshold on Port 1
❐
Hot Swap Capability on all Port 1 GPIO
■
Versatile Analog Mux
❐
Common Internal Analog Bus
❐
Simultaneous Connection of I/O
❐
High PSRR Comparator
❐
Low Dropout Voltage Regulator for All Analog Resources
Additional System Resources
❐
I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• No Clock Stretching Required (under most conditions)
• Implementation During Sleep Modes with Less Than
100 µA
• Hardware Address Validation
❐
SPI™ Master and Slave: Configurable 46.9 kHz to 12 MHz
❐
Three 16-Bit Timers
❐
Watchdog and Sleep Timers
❐
Internal Voltage Reference
❐
Integrated Supervisory Circuit
❐
8-bit Delta-Sigma Analog-to-Digital Converter
❐
Two General Purpose High Speed, Low Power Analog
Comparators
Complete Development Tools
❐
Free Development Tool (PSoC Designer™)
❐
Full Featured, In-Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Trace Memory
Package Options
❐
CY8C20x36:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 x 7 x 1.0 mm QFN
❐
CY8C20x46:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
❐
CY8C20x96:
• 24-Pin 4 x 4 x 0.6 mm QFN (with USB)
• 32-Pin 5 x 5 x 0.6 mm QFN (with USB)
❐
CY8C20x66:
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
• 48-Pin SSOP
■
■
■
■
■
■
■
■
Cypress Semiconductor Corporation
Document Number: 001-12696 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 09, 2009
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CY8C20X36/46/66/96
Logic Block Diagram
Port 4
Port 3
Port 2
Port 1
Port 0
1.8/2.5/3V
LDO
PWRSYS
(Regulator)
PSoC CORE
SYSTEM BUS
Global Analog Interconnect
1K/2K
SRAM
Interrupt
Controller
Supervisory ROM (SROM)
8K/16K/32K Flash
Nonvolatile Memory
Sleep and
Watchdog
CPU Core (M8C)
6/12/24 MHz Internal Main Oscillator
(IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE
SYSTEM
Two
Comparators
CapSense
Module
Analog
Reference
Analog
Mux
SYSTEM BUS
USB
I2C
Slave
Internal
Voltage
References
System
Resets
POR
and
LVD
SPI
Master/
Slave
Three 16-Bit
Programmable
Timers
Digital
Clocks
SYSTEM RESOURCES
Document Number: 001-12696 Rev. *F
Page 2 of 39
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CY8C20X36/46/66/96
PSoC
®
Functional Overview
The PSoC family consists of on-chip Controller devices. These
devices are designed to replace multiple traditional MCU-based
components with one, low cost single-chip programmable
component. A PSoC device includes configurable analog and
digital blocks, and programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
The architecture for this device family, as shown in the
Logic
Block Diagram on page 2,
is comprised of three main areas: the
Core, the CapSense Analog System, and the System Resources
(including a full speed USB port). A common, versatile bus allows
connection between I/O and the analog system. Each
CY8C20x36/46/66/96 PSoC Device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 36 general purpose IO (GPIO) are also
included. The GPIO provides access to the MCU and analog
mux.
Figure 1. Analog System Block Diagram
IDAC
Analog Global Bus
Vr
Reference
Buffer
Cinternal
Comparator
Mux
Mux
Refs
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard archi-
tecture microprocessor.
System Resources provide additional capability, such as
configurable USB and I2C slave/SPI master-slave
communication interface, three 16-bit programmable timers, and
various system resets supported by the M8C.
The Analog System is composed of the CapSense PSoC block
and an internal 1.2V analog reference, which together support
capacitive sensing of up to 36 inputs.
CapSenseCounters
CSCLK
IMO
CapSense
Clock Select
Oscillator
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
■
■
CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins are
completed quickly and easily across multiple ports.
Complex capacitive sensing interfaces, such as sliders and
touchpads.
Chip-wide mux that allows analog input from any I/O pin.
Crosspoint connection between any I/O pin combinations.
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under
http://www.cypress.com
>
Documentation > Application Notes. In general, and unless
otherwise noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.
Document Number: 001-12696 Rev. *F
Page 3 of 39
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CY8C20X36/46/66/96
Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include low voltage detection and
power on reset. The merits of each system resource are listed
here:
■
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming
details, see the PSoC
®
Programmable System-on-Chip™
Technical Reference Manual for CY8C20x36/46/66/96 PSoC
Devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at
www.cypress.com/psoc.
The I2C slave/SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
The I2C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power-On-Reset) circuit eliminates the need for a system
supervisor.
An internal reference provides an absolute reference for capac-
itive sensing.
A register-controlled bypass mode allows the user to disable
the LDO.
Standard Cypress PSoC IDE tools are available for debugging
the CY8C20x36/46/66/96 family of parts. However, the
additional trace length and a minimal ground plane in the Flex-
Pod can create noise problems that make it difficult to debug
the design. A custom bonded On-Chip Debug (OCD) device is
available in an 48-pin QFN package. The OCD device is
recommended for debugging designs that have high current
and/or high analog accuracy requirements. The QFN package
is compact and is connected to the ICE through a high density
connector.
■
■
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc.
Select Application Notes under the
Documentation tab.
■
■
■
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop
and through a growing number of
regional and global distributors, which include Arrow, Avnet, Digi-
Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at
www.cypress.com/training.
The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to
www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions.
Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at
www.cypress.com/support.
If you cannot
find an answer to your question, call technical support at 1-800-
541-4736.
Document Number: 001-12696 Rev. *F
Page 4 of 39
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CY8C20X36/46/66/96
Development Tools
PSoC Designer is a Microsoft
®
Windows-based, integrated
development environment for the Programmable System-on-
Chip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows XP and Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assem-
blers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers.
The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers.
C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
PSoC Designer Software Subsystems
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Express. In this
view you solve design problems the same way you might think
about the system. Select input and output devices based upon
system requirements. Add a communication interface and define
the interface to the system (registers). Define when and how an
output device changes state based upon any/all other system
devices. Based upon the design, PSoC Designer automatically
selects one or more PSoC devices that match your system
requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.x. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over on-
chip resources. All views of the project share common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-12696 Rev. *F
Page 5 of 39
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