CY7C68023/CY7C68024
EZ-USB NX2LP™ USB 2.0 NAND Flash
Controller
EZ-USB NX2LP™ USB 2.0 NAND Flash Controller
Features
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43 mA Typical Active Current
Space Saving and Pb-free 56-QFN Package (8 mm × 8 mm)
Support for Board-level Manufacturing test through USB
Interface
3.3 V NAND Flash Operation
NAND Flash Power Management Support
High (480-Mbps) or Full (12-Mbps) Speed USB Support
Both Common NAND Page Sizes Supported
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512 bytes — Up to 1 Gbit Capacity
❐
2K bytes — Up to 8 Gbit Capacity
Eight Chip Enable Pins
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Up to 8 NAND Flash Single Device Chips
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Up to 4 NAND Flash Dual Device Chips
Industry Standard ECC NAND Flash Correction
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1 bit per 256 correction
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2 bit error detection
Industry Standard (SmartMedia) Page Management for Wear
Leveling Algorithm, Bad Block Handling, and Physical to
Logical management
Supports 8-bit NAND Flash Interfaces
Supports 30 ns, 50 ns, and 100 ns NAND Flash Timing
Complies with USB Mass Storage Class Specification rev 1.0
CY7C68024 Complies with USB 2.0 Specification for
Bus-Powered Devices (TID# 40460274)
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Introduction
The EZ-USB NX2LPNX2LPimplements a USB 2.0 NAND
Flash controller. This controller adheres to the
Mass Storage
Class Bulk-Only Transport Specification.
The USB port of the
NX2LP is connected to a host computer directly or through the
downstream port of a USB hub. Host software issues commands
and data to the NX2LP and receives status and data from the
NX2LP using standard USB protocol.
The NX2LP supports industry leading 8-bit NAND Flash
interfaces and both common NAND page sizes of 512 and 2k
bytes. Eight chip enable pins allow the NX2LP to be connected
to up to eight single or four dual device NAND Flash chips.
Certain NX2LP features are configurable, enabling the NX2LP to
meet the needs of different design requirements.
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NX2LP Block Diagram
Chip Reset
Write Protect
LED2#
24 MHz
Xtal
LED1#
PLL
EZ-USB NX2LP
Internal Control Logic
Control
NAND Control Signals
NAND Flash
Interface
Logic
Chip Enable Signals
VBUS
D+
D-
USB 2.0
Xceiver
Smart HS/
FS USB
Engine
Data
8-bit Data Bus
Cypress Semiconductor Corporation
Document #: 38-08055 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 29, 2011
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CY7C68023/CY7C68024
Pin Assignments
Figure 1. 56-pin QFN
Reserved
44
CE7#
CE6#
CE5#
CE4#
CE3#
CE2#
CE1#
CE0#
45
GND
GND
VCC
56
55
54
53
52
51
50
49
48
47
46
R_B1#
R_B2#
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
N/C
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
27
21
28
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VCC
N/C
RESET#
GND
N/C
N/C
WP_SW#
WP_NF#
LED2#
LED1#
ALE
CLE
VCC
RE1#
RE0#
WE#
GND
Reserved
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Name
R_B1#
[1]
R_B2#
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
N/C
GND
Reserved
Type
I
I
PWR
Xtal
Xtal
GND
PWR
I/O
I/O
GND
PWR
GND
N/A
GND
N/A
Default State at Startup
Z
Z
PWR
N/A
N/A
GND
PWR
Z
Z
GND
PWR
GND
N/A
GND
N/A
Description
Ready/Busy 1 (2.2k to 4k pull up resistor is required)
Ready/Busy 2 (2.2k to 4k pull up resistor is required)
Analog 3.3 V supply
Crystal output
Crystal input
Ground
Analog 3.3 V supply
USB D+
USB D-
Ground
3.3 V supply
Ground
No connect
Ground
Must be tied HIGH (no pull up resistor required)
Note
1. A # sign after the pin name indicates that it is an active LOW signal.
Document #: 38-08055 Rev. *E
Reserved
GND
VCC
VCC
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
Page 2 of 10
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CY7C68023/CY7C68024
Pin Descriptions
(continued)
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Name
Reserved
VCC
DDO
DD1
DD2
DD3
DD4
DD5
DD6
DD7
GND
VCC
GND
WE#
RE0#
RE1#
VCC
CLE
ALE
LED1#
LED2#
WP_NF#
WP_SW#
N/C
N/C
GND
RESET#
VCC
Reserved
CE0#
CE1#
CE2#
CE3#
CE4#
CE5#
CE6#
CE7#
GND
N/C
VCC
GND
Type
N/A
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
PWR
GND
O
O
O
PWR
O
O
O
O
O
I
N/A
N/A
GND
I
PWR
N/A
O
O
O
O
O
O
O
O
GND
N/A
PWR
GND
Default State at Startup
N/A
PWR
Z
Z
Z
Z
Z
Z
Z
Z
GND
PWR
GND
H
H
H
PWR
Z
Z
Z
Z
Z
Z
N/A
N/A
GND
Z
PWR
N/A
Z
Z
Z
Z
Z
Z
Z
Z
GND
N/A
PWR
GND
Description
Must be tied HIGH (no pull up resistor required)
3.3 V supply
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Ground
3.3 V supply
Ground
Write enable
Read Enable 0
Read Enable 1
3.3 V supply
Command latch enable
Address latch enable
Data activity LED sink
Chip active LED sink
Write-protect NAND Flash
Write-protect switch input
No connect
No connect
Ground
NX2LP chip reset
3.3 V supply
Must be tied HIGH
Chip enable 0
Chip enable 1
Chip enable 2
Chip enable 3
Chip enable 4
Chip enable 5
Chip enable 6
Chip enable 7
Ground
No connect
3.3 V supply
Ground
Document #: 38-08055 Rev. *E
Page 3 of 10
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CY7C68023/CY7C68024
Additional Pin Descriptions
DPLUS, DMINUS
DPLUS and DMINUS are the USB signaling pins, and they
should be tied to the D+ and D– pins of the USB connector.
Because they operate at high frequencies, the USB signals
require special consideration when designing the layout of the
PCB. General guidelines are given at the end of this document.
Figure 2. XTALIN, XTALOUT Diagram
CLE
The Command Latch Enable output pin is used to indicate that
the data on the I/O bus is a command. The data is latched into
the NAND Flash control register on the rising edge of WE# when
CLE is HIGH.
ALE
The Address Latch Enable output pin is used to indicate that the
data on the I/O bus is an address. The data is latched into the
NAND Flash address register on the rising edge of WE# when
ALE is HIGH.
LED1#
The Data Activity LED output pin is used to indicate data transfer
activity. LED1# is asserted LOW at the beginning of a data
transfer, and set to a high Z state when the transfer is complete.
If this functionality is not utilized, leave LED1# floating.
LED2#
The Chip Active LED output pin is used to indicate proper device
operation. LED2# is asserted LOW when the NX2LP is powered
and initialized. It is placed in a high Z state under all other
conditions. If this functionality is not used, leave LED2# floating.
WP_NF#
XTALIN
XTALOUT
24-MHz Xtal
12 pF
12 pF
12-pF capacitor
values assume a
trace capacitance
of 3 pF per side on a
four-layer FR4 PCB
The NX2LP requires a 24 MHz (±100 ppm) signal to derive
internal timing. Typically, a 24 MHz (20 pF, 500
W,
parallel-resonant fundamental mode) crystal is used, but a
24 MHz square wave from another source can also be used. If a
crystal is used, connect its pins to XTALIN and XTALOUT, and
also through 12 pF capacitors to GND. If an alternate clock
source is used, apply it to XTALIN and leave XTALOUT open.
Data[7-0]
The Data[7-0] I/O pins provide an 8-bit interface to a NAND Flash
device. These pins are used to transfer address, command, and
read/write data between the NX2LP and NAND Flash.
R_B[2-1]#
The Ready/Busy input pins are used to determine the state of the
currently selected NAND Flash device. These pins must be
pulled HIGH through a 2k-4k resistor. These pins are pulled LOW
by the NAND Flash when it is busy.
WE#
The Write Enable output pin is used by the NAND Flash to latch
commands, address, and data during the rising edge of the
pulse.
RE[1-0]#
The Read Enable output pins are used to control the data flow
from the NAND Flash devices. The device presents valid data
and increments its internal column address counter by one step
on each falling edge of the Read Enable pulse. A 10k pull up is
an option For RE1-0#.
The Write-protect NAND Flash output pin is used to control the
write-protect pins on NAND Flash devices. This pin should be
tied to the Write Protect pins of the NAND Flash devices. If
WP_SW# is asserted LOW during a data transfer, or if internal
operations are still pending, the NX2LP waits until the operation
is complete before asserting WP_NF# to ensure that there is no
data loss or risk of OS error.
WP_SW#
The Write-protect Switch input pin is used to select whether or
not NAND Flash write-protection is enabled by the NX2LP. When
the pin is asserted LOW, the NX2LP reports to the host that the
NAND Flash is write-protected, the WP_NF# is driven LOW, and
any attempts to write to the configuration data memory area are
blocked by the NX2LP. If this pin is asserted LOW during a data
transfer, or if internal operations are still pending, the NX2LP
waits until the operation is complete before asserting WP_NF#
to ensure that there is no data loss or risk of OS error.
CE[7-0]#
The Chip Enable output pins are used to select the NAND Flash
that the NX2LP interfaces. Unused Chip Enable pins should be
left floating.
RESET#
Asserting RESET# for 10 ms resets the NX2LP. A reset and/or
watchdog chip is recommended to ensure that startup and
brownout conditions are properly handled.
Document #: 38-08055 Rev. *E
Page 4 of 10
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CY7C68023/CY7C68024
Applications
The NX2LP is a high speed USB 2.0 peripheral device that
connects NAND Flash devices to a USB host using the USB
Mass Storage Class protocol.
Manufacturing Mode
In Manufacturing mode, the NX2LP enumerates using the
default descriptors and configuration data that are stored in
internal ROM. This mode enables first-time programming of the
configuration data memory area, and board-level manufacturing
tests.
A unique USB serial number is required for each device in order
to comply with the USB Mass Storage specification. Cypress
also requires designers to use their own Vendor ID for final
products. The Vendor ID is obtained through registration with the
USB Implementor’s Forum (USB-IF), and the Product ID is
determined by the designer.
Cypress provides all the software tools and drivers necessary for
properly programming and testing the NX2LP. Refer to the
documentation in the development or reference design kit for
more information on these topics.
Figure 3. NX2LP Enumeration Process
Start-up
Additional Resources
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CY3685 EZ-USB NX2LP Development Kit
CY4618 EZ-USB NX2LP Reference Design Kit
USB Specification version 2.0
USB
Mass Storage Class Bulk Only Transport Specification,
http://www.usb.org/devel-
opers/devclass_docs/usbmassbulk_10.pdf .
Functional Overview
USB Signaling Speed
The NX2LP operates at two of the three rates defined in the USB
Specification Revision 2.0 dated April 27, 2000:
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Full speed, with a signaling bit rate of 12 Mbits/sec
High speed, with a signaling bit rate of 480 Mbits/sec.
Yes
NAND Flash
Present?
No
The NX2LP does not support the low speed signaling rate of
1.5 Mbits/sec.
NAND Flash Interface
During normal operation the NX2LP supports an 8-bit I/O
interface, eight chip enable pins, and other control signals
compatible with industry standard NAND Flash devices.
Enumeration
During the startup sequence, internal logic checks for the
presence of NAND Flash with valid configuration data in the
configuration data memory area. If valid configuration data is
found, the NX2LP uses the values stored in NAND Flash to
configure the USB descriptors for normal operation as a USB
mass storage device. If no NAND Flash is detected, or if no valid
configuration data is found in the configuration data memory
area, the NX2LP uses the default values from internal ROM
space for manufacturing mode operation. The two modes of
operation are described in the following sections.
NAND Flash
Programmed?
No
Yes
Load Custom
Descriptors and
Configuration Data
Load Default
Descriptors and
Configuration Data
Normal Operation Mode
In Normal Operation Mode, the NX2LP behaves as a USB 2.0
Mass Storage Class NAND Flash controller. This includes all
typical USB device states (powered, configured, and so on). The
USB descriptors are returned according to the data stored in the
configuration data memory area. Normal read and write access
to the NAND Flash is available in this mode.
Enumerate As
USB Mass
Storage Device
Enumerate As
Generic NX2LP
Device
Normal Operation
Mode
Manufacturing
Mode
Document #: 38-08055 Rev. *E
Page 5 of 10
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