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CY7C1021CV26-15ZSXE

产品描述1-Mbit (64 K x 16) Static RAM CMOS for optimum speed/power
文件大小452KB,共16页
制造商Cypress(赛普拉斯)
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CY7C1021CV26-15ZSXE概述

1-Mbit (64 K x 16) Static RAM CMOS for optimum speed/power

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CY7C1021CV26
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
Features
automatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into
the location specified on the address pins (A
0
through A
15
). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into the location specified on the address
pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then
data from memory will appear on I/O
8
to I/O
15
. See the truth table
at the end of this data sheet for a complete description of Read
and Write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a Write operation (CE
LOW, and WE LOW).
Temperature Range
Automotive: –40 °C to 125 °C
High speed
t
AA
= 15 ns
Optimized voltage range: 2.5 V to 2.7 V
Low active power: 220 mW (Max)
Automatic power-down when deselected
Independent control of upper and lower bits
CMOS for optimum speed/power
Available in Pb-free and non Pb-free 44-pin TSOP II, 44-pin
(400-Mil) Molded SOJ and Pb-free 48-ball FBGA packages
Functional Description
The CY7C1021CV26 is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
64 K × 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
Cypress Semiconductor Corporation
Document Number: 38-05589 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 20, 2011
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