CY14V101LA
CY14V101NA
1-Mbit (128 K × 8/64 K × 16) nvSRAM
1-Mbit (128 K × 8/64 K × 16) nvSRAM
Features
■
■
■
■
■
■
■
■
■
■
■
■
Functional Description
The Cypress CY14V101LA/CY14V101NA is a fast static RAM,
with a non-volatile element in each memory cell. The memory is
organized as 128 K bytes of 8 bits each or 64 K words of 16 bits
each. The embedded non-volatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
non-volatile memory. The SRAM provides infinite read and write
cycles, while independent non-volatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power down. On power-up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control.
25 ns and 45 ns access times
Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16
(CY14V101NA)
Hands off automatic STORE on power down with only a small
capacitor
STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power down
RECALL to SRAM initiated by software or power up
Infinite read, write, and recall cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Core V
CC
= 3.0 V to 3.6 V; I/O V
CCQ
= 1.65 V to 1.95 V
Industrial temperature
48-ball fine-pitch ball grid array (FBGA) package
Pb-free and restriction of hazardous substances (RoHS)
compliance
Logic Block Diagram
[1, 2, 3]
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
R
O
W
D
E
C
O
D
E
R
Quatrum Trap
1024 X 1024
STORE
RECALL
STATIC RAM
ARRAY
1024 X 1024
STORE/RECALL
CONTROL
HSB
V
CC
V
CCQ
V
CAP
POWER
CONTROL
SOFTWARE
DETECT
A
14
- A
2
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
A
0
A
1
A
2
A
3
A
4
A
10
A
11
CE
BLE
I
N
P
U
T
B
U
F
F
E
R
S
COLUMN I/O
COLUMN DEC
OE
WE
BHE
Notes
1. Address A
0
–A
16
for × 8 configuration and Address A
0
–A
15
for × 16 configuration.
2. Data DQ
0
–DQ
7
for × 8 configuration and Data DQ
0
–DQ
15
for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-53953 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 4, 2011
[+] Feedback
CY14V101LA
CY14V101NA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
AutoStore Operation ........................................................ 4
Hardware STORE Operation ............................................ 4
Hardware RECALL (Power-Up) ....................................... 5
Software STORE ............................................................... 5
Software RECALL ............................................................. 5
Preventing AutoStore ....................................................... 6
Data Protection ................................................................. 6
Noise Considerations ....................................................... 6
Best Practices ................................................................... 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
DC Electrical Characteristics .......................................... 8
Data Retention and Endurance ....................................... 9
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Loads ................................................................ 10
AC Test Conditions ........................................................ 10
AC Switching Characteristics ....................................... 11
SRAM Read Cycle .................................................... 11
SRAM Write Cycle ..................................................... 11
Switching Waveforms .................................................... 11
AutoStore/Power-up RECALL ....................................... 14
Switching Waveforms .................................................... 14
Software Controlled STORE/RECALL Cycle ................ 15
Switching Waveforms .................................................... 15
Hardware STORE Cycle ................................................. 16
Switching Waveforms .................................................... 16
Truth Table For SRAM Operations ................................ 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Document #: 001-53953 Rev. *H
Page 2 of 22
[+] Feedback
CY14V101LA
CY14V101NA
Pinouts
Figure 1. Pin Diagram – 48-ball FBGA
(× 8)
(× 16)
Top View
(not to scale)
1
NC
NC
DQ
0
V
SS
V
CCQ
DQ
3
NC
[5]
NC
Top View
(not to scale)
6
V
CC
NC
DQ
4
V
CCQ
V
SS
DQ
7
NC
NC
[6]
2
OE
NC
NC
DQ
1
DQ
2
NC
HSB
A
8
3
A
0
A
3
A
5
[4]
NC
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
NC
DQ
5
DQ
6
NC
WE
A
11
1
A
B
C
D
E
F
G
H
2
OE
BHE
3
A
0
A
3
A
5
4
A
1
A
4
A
6
A
7
5
A
2
CE
DQ
1
6
V
CC
DQ
0
DQ
2
A
B
C
D
E
F
G
H
BLE
DQ
8
DQ
9
DQ
10
V
SS
[5]
DQ
11
NC
DQ
3
V
CCQ
V
SS
DQ
6
DQ
7
NC
V
CAP
A
14
A
12
A
9
V
CCQ
DQ
12
DQ
14
DQ
13
DQ
15
HSB
NC
[6]
[4]
V
CAP
NC
DQ
4
A
14
A
12
A
9
A
15
A
13
A
10
DQ
5
WE
A
11
A
8
Pin Definitions
Pin Name
I/O Type
Description
Address inputs. Used to select one of the 131,072 bytes of the nvSRAM for × 8 configuration.
A
0
–A
16
Input
A
0
–A
15
Address inputs. Used to select one of the 65,536 words of the nvSRAM for × 16 configuration.
Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
DQ
0
–DQ
7
Input/Output
DQ
0
–DQ
15
Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation.
WE
Input
Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Input
Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
Input
Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles.
OE
I/O pins are tri-stated on deasserting OE HIGH.
Input
Byte high enable, active LOW. Controls DQ
15
–DQ
8
.
BHE
Input
Byte low enable, active LOW. Controls DQ
7
–DQ
0
.
BLE
V
SS
Ground
Ground for the device. Must be connected to the ground of the system.
V
CC
Power supply Power supply inputs to the core of the device.
V
CCQ
Power supply Power supply inputs for the inputs and outputs of the device.
HSB
Input/Output Hardware STORE busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a non-volatile STORE operation. After each hardware
and software STORE operation HSB is driven HIGH for a short time (t
HHHD
) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
No connect No connect. This pin is not connected to the die.
V
CAP
NC
Notes
4. Address expansion for 2-Mbit. NC pin not connected to die.
5. Address expansion for 4-Mbit. NC pin not connected to die.
6. Address expansion for 8-Mbit. NC pin not connected to die.
Document #: 001-53953 Rev. *H
Page 3 of 22
[+] Feedback
CY14V101LA
CY14V101NA
Device Operation
The CY14V101LA/CY14V101NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a non-volatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the non-volatile cell (the STORE
operation), or from the non-volatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations, SRAM read and write operations are inhibited. The
CY14V101LA/CY14V101NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the non-volatile cells and up to 1 million STORE
operations. Refer to the
Truth Table For SRAM Operations on
page 17
for a complete description of read and write modes.
AutoStore on page 6.
If AutoStore is enabled without a capacitor
on V
CAP
pin, the device attempts an AutoStore operation without
sufficient charge to complete the Store. This corrupts the data
stored in nvSRAM.
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for automatic STORE operation. Refer to
DC Electrical
Characteristics on page 8
for the size of V
CAP
. The voltage on
the V
CAP
pin is driven to V
CC
by a regulator on the chip. Place a
pull-up on WE to hold it inactive during power up. This pull-up is
only effective if the WE signal is tristate during power up. Many
MPUs tristate their controls on power-up. This must be verified
when using the pull-up. When the nvSRAM comes out of
power-on-RECALL, the MPU must be active or the WE held
inactive until the MPU comes out of reset.
To reduce unnecessary non-volatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 2. AutoStore Mode
V
CCQ
V
CC
SRAM Read
The CY14V101LA/CY14V101NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A
0–16
or A
0–15
determines which of the 131,072
data bytes or 65,536 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t
AA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t
ACE
or at t
DOE
, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
t
AA
access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0.1 uF
10 kOhm
V
CCQ
V
CC
0.1 uF
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ
0–15
are written into the memory if the data is valid t
SD
before the end
of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers t
HZWE
after WE goes LOW.
WE
V
CAP
V
CAP
V
SS
AutoStore Operation
The CY14V101LA/CY14V101NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by HSB; Software STORE activated by an
address sequence; AutoStore on device power down. The
AutoStore operation is a unique feature of QuantumTrap
technology
and
is
enabled
by
default
on
the
CY14V101LA/CY14V101NA.
During a normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Note
If a capacitor is not connected to V
CAP
pin, AutoStore must
be disabled using the soft sequence specified in
Preventing
Document #: 001-53953 Rev. *H
Hardware STORE Operation
The CY14V101LA/CY14V101NA provides the HSB pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14V101LA/CY14V101NA conditionally initiates a
STORE operation after t
DELAY
. An actual STORE cycle only
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 k weak pull-up resistor) that is
internally driven LOW to indicate a busy condition when the
STORE (initiated by any means) is in progress.
Note
After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t
HHHD
) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
Page 4 of 22
[+] Feedback
CY14V101LA
CY14V101NA
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (t
DELAY
) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14V101LA/CY14V101NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
During any STORE operation, regardless of how it is initiated,
the CY14V101LA/CY14V101NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for t
LZHSB
time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the t
STORE
cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Hardware RECALL (Power-Up)
During power up or after any low power condition
(V
CC
< V
SWITCH
), an internal RECALL request is latched. When
V
CC
again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle is automatically initiated and takes t
HRECALL
to complete.
During this time, HSB is driven LOW by the HSB driver.
Software RECALL
Data is transferred from the non-volatile memory to the SRAM
by a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the non-volatile information is transferred into
the SRAM cells. After the t
RECALL
cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
Software STORE
Data is transferred from the SRAM to the non-volatile memory
by
a
software
address
sequence.
The
CY14V101LA/CY14V101NA Software STORE cycle is initiated
by executing sequential CE or OE controlled read cycles from six
specific address locations in exact order. During the STORE
cycle an erase of the previous non-volatile data is first performed,
followed by a program of the non-volatile elements. After a
STORE cycle is initiated, further input and output are disabled
until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
Table 1. Mode Selection
CE
H
L
L
L
WE
X
H
L
H
OE
X
L
X
L
BHE, BLE
[7]
X
L
L
X
A
15
–A
0
[8]
X
X
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Mode
Not selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
I/O
Output High Z
Output data
Input data
Output data
Output data
Output data
Output data
Output data
Output data
Power
Standby
Active
Active
Active
[9]
Notes
7. BHE and BLE are applicable for x16 configuration only.
8. While there are 17 address lines on the CY14V101LA (16 address lines on the CY14V101NA), only the 13 address lines (A
14
–A
2
) are used to control software modes.
Rest of the address lines are don’t care.
9. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document #: 001-53953 Rev. *H
Page 5 of 22
[+] Feedback
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
