CY14B101LA
CY14B101NA
1-Mbit (128 K × 8/64 K × 16) nvSRAM
1-Mbit (128 K × 8/64 K × 16) nvSRAM
Features
■
■
■
■
■
■
■
■
■
■
■
20 ns, 25 ns, and 45 ns access times
Internally organized as 128 K × 8 (CY14B101LA) or 64 K × 16
(CY14B101NA)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Single 3 V +20% to –10% operation
Industrial temperature
■
Packages
❐
32-pin small-outline integrated circuit (SOIC)
❐
44-/54-pin thin small outline package (TSOP) Type II
❐
48-pin shrink small-outline package (SSOP)
❐
48-ball fine-pitch ball grid array (FBGA)
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B101LA/CY14B101NA is a fast static RAM
(SRAM), with a nonvolatile element in each memory cell. The
memory is organized as 128 K bytes of 8 bits each or 64 K words
of 16 bits each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
Logic Block Diagram
[1, 2, 3]
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
R
O
W
D
E
C
O
D
E
R
Quatrum Trap
1024 X 1024
STORE
RECALL
STATIC RAM
ARRAY
1024 X 1024
STORE/RECALL
CONTROL
HSB
V
CC
V
CAP
POWER
CONTROL
SOFTWARE
DETECT
A
14
- A
2
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
A
0
A
1
A
2
A
3
A
4
A
10
A
11
CE
BLE
I
N
P
U
T
B
U
F
F
E
R
S
COLUMN I/O
COLUMN DEC
OE
WE
BHE
Notes
1. Address A
0
–A
16
for × 8 configuration and Address A
0
–A
15
for × 16 configuration.
2. Data DQ
0
–DQ
7
for × 8 configuration and Data DQ
0
–DQ
15
for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-42879 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 14, 2011
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CY14B101LA
CY14B101NA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 5
Device Operation .............................................................. 6
SRAM Read ....................................................................... 6
SRAM Write ....................................................................... 6
AutoStore Operation ........................................................ 6
Hardware STORE Operation ............................................ 6
Hardware RECALL (Power-up) ........................................ 7
Software STORE ............................................................... 7
Software RECALL ............................................................. 7
Preventing AutoStore ....................................................... 8
Data Protection ................................................................. 8
Noise Considerations ....................................................... 8
Best Practices ................................................................... 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
DC Electrical Characteristics ........................................ 10
Data Retention and Endurance ..................................... 11
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads ................................................................ 11
AC Test Conditions ........................................................ 11
AC Switching Characteristics ....................................... 12
SRAM Read Cycle .................................................... 12
SRAM Write Cycle ..................................................... 12
Switching Waveforms .................................................... 12
AutoStore/Power-Up RECALL ....................................... 15
Switching Waveforms .................................................... 15
Software Controlled STORE/RECALL Cycle ................ 16
Switching Waveforms .................................................... 16
Hardware STORE Cycle ................................................. 17
Switching Waveforms .................................................... 17
Truth Table For SRAM Operations ................................ 18
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 20
Package Diagrams .......................................................... 21
Acronyms ........................................................................ 25
Document Conventions ............................................. 25
Units of Measure ....................................................... 25
Document History Page ................................................. 26
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC Solutions ......................................................... 28
Document #: 001-42879 Rev. *L
Page 2 of 28
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CY14B101LA
CY14B101NA
Pinouts
Figure 1. Pin Diagram – 44-pin TSOP II
NC
[7]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
V
CC
V
SS
DQ
2
DQ
3
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
[6]
NC
[5]
NC
[4]
NC
A
16
A
15
OE
DQ
7
DQ
6
V
SS
V
CC
DQ
5
DQ
4
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
[5]
[4]
NC
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
44-pin TSOP II
(× 8)
44-pin TSOP II
(× 16)
[8]
Top View
(not to scale)
Top View
(not to scale)
Figure 2. Pin Diagram – 48-pin SSOP and 32-pin SOIC
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
NC
A
4
NC
NC
NC
V
SS
NC
NC
DQ0
A
3
A
2
A
1
A
0
DQ1
DQ2
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
A
15
HSB
WE
A
13
A
8
A
9
NC
A
11
NC
NC
NC
V
SS
NC
NC
DQ6
OE
A
10
CE
DQ7
DQ5
DQ4
DQ3
V
CC
48-pin SSOP
(×8)
32-pin SOIC
Top View
(not to scale)
(×8)
(x8)
Top View
(not to scale)
Notes
4. Address expansion for 2-Mbit. NC pin not connected to die.
5. Address expansion for 4-Mbit. NC pin not connected to die.
6. Address expansion for 8-Mbit. NC pin not connected to die.
7. Address expansion for 16-Mbit. NC pin not connected to die.
8. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document #: 001-42879 Rev. *L
Page 3 of 28
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CY14B101LA
CY14B101NA
Pinouts
(continued)
Figure 3. 48-ball FBGA and 54-pin TSOP II
48-FBGA
(x8)
Top View
(not to scale)
1
NC
NC
DQ
0
V
SS
V
CC
DQ
3
NC
2
OE
NC
NC
DQ
1
DQ
2
NC
HSB
3
A
0
A
3
A
5
[9]
NC
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
NC
DQ
5
DQ
6
NC
WE
A
11
6
NC
NC
DQ
4
V
CC
V
SS
DQ
7
NC
NC
[11]
A
B
C
D
E
F
G
H
NC
[12]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
NC
V
CAP
A
14
A
12
A
9
[10]
A
8
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
54 - TSOP II
(x16)
Top View
(
not to scale)
HSB
NC
[11]
[10]
NC
[9]
NC
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
NC
NC
Notes
9. Address expansion for 2-Mbit. NC pin not connected to die.
10. Address expansion for 4-Mbit. NC pin not connected to die.
11. Address expansion for 8-Mbit. NC pin not connected to die.
12. Address expansion for 16-Mbit. NC pin not connected to die.
Document #: 001-42879 Rev. *L
Page 4 of 28
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CY14B101LA
CY14B101NA
Pin Definitions
Pin Name
A
0
–A
16
A
0
–A
15
DQ
0
–DQ
7
DQ
0
–DQ
15
WE
CE
OE
BHE
BLE
V
SS
V
CC
HSB
[13]
I/O Type
Input
Input/Output
Input
Input
Input
Input
Input
Ground
Description
Address inputs. Used to select one of the 131,072 bytes of the nvSRAM for × 8 configuration.
Address inputs. Used to select one of the 65,536 words of the nvSRAM for × 16 configuration.
Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
Bidirectional Data I/O Lines for × 16 configuration. Used as input or output lines depending on operation.
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tristated on deasserting OE HIGH.
Byte High Enable, Active LOW. Controls DQ
15
–DQ
8
.
Byte Low Enable, Active LOW. Controls DQ
7
–DQ
0
.
Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the device. 3.0 V +20%, –10%
Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (t
HHHD
) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No connect
No connect. This pin is not connected to the die.
V
CAP
NC
Note
13. HSB pin is not available in 44-pin TSOP II (× 16) package.
Document #: 001-42879 Rev. *L
Page 5 of 28
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