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CY62148DV30L-70BVIT: 产品描述Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36; 产品类别存储存储; 文件大小182KB，共11页; 制造商Cypress(赛普拉斯)

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CY62148DV30L-70BVIT概述

Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36

CY62148DV30L-70BVIT规格参数

参数名称	属性值
厂商名称	Cypress(赛普拉斯)
零件包装代码	BGA
包装说明	6 X 8 MM, 1 MM HEIGHT, VFBGA-36
针数	36
Reach Compliance Code	unknown
ECCN代码	3A991.B.2.A
最长访问时间	70 ns
JESD-30 代码	R-PBGA-B36
JESD-609代码	e0
长度	8 mm
内存密度	4194304 bit
内存集成电路类型	STANDARD SRAM
内存宽度	8
功能数量	1
端子数量	36
字数	524288 words
字数代码	512000
工作模式	ASYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	512KX8
封装主体材料	PLASTIC/EPOXY
封装代码	VFBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行	PARALLEL
认证状态	Not Qualified
座面最大高度	1 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	2.2 V
标称供电电压 (Vsup)	3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	TIN LEAD
端子形式	BALL
端子节距	0.75 mm
端子位置	BOTTOM
宽度	6 mm
Base Number Matches	1

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CY62148DV30

4-Mb (512K x 8) MoBL



Static RAM

Features

• Very high speed: 55 ns

— Wide voltage range: 2.20V – 3.60V

• Pin-compatible with CY62148CV25, CY62148CV30 and

CY62148CV33

• Ultra low active power

— Typical active current: 1.5 mA @ f = 1 MHz

•

— Typical active current: 8 mA @ f = f

max

(55-ns speed)

Ultra low standby power

Easy memory expansion with CE, and OE features

Automatic power-down when deselected

CMOS for optimum speed/power

Packages offered: 36-ball BGA, 32-pin TSOPII and

32-pin SOIC

Functional Description

[1]

The CY62148DV30 is a high-performance CMOS static RAMs

organized as 512K words by 8 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL



) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

reduces power consumption. The device can be put into

standby mode reducing power consumption when deselected

(CE HIGH).

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O

through I/O

) is then written into the location

specified on the address pins (A

through A

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

The eight input/output pins (I/O

through I/O

) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW and WE LOW).

Logic Block Diagram

Data in Drivers

I/O

ROW DECODER

SENSE AMPS

I/O

512K x 8

ARRAY

COLUMN

DECODER

POWER

DOWN

I/O

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05341 Rev. *B

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised February 10, 2004

CY62148DV30L-70BVIT相似产品对比

	CY62148DV30L-70BVIT	CY62148DV30L-55SXIT	CY62148DV30LL-70BVIT	CY62148DV30L-55BVXIT	CY62148DV30L-70ZSXIT	CY62148DV30L-70BVXIT	CY62148DV30LL-70SXIT	CY62148DV30L-70SXIT	CY62148DV30LL-70BVXIT
描述	Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36	Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32	Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36	Standard SRAM, 512KX8, 55ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36	Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, LEAD FREE, TSOP2-32	Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36	Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32	Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32	Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36
零件包装代码	BGA	SOIC	BGA	BGA	TSOP2	BGA	SOIC	SOIC	BGA
包装说明	6 X 8 MM, 1 MM HEIGHT, VFBGA-36	SOP,	6 X 8 MM, 1 MM HEIGHT, VFBGA-36	6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36	TSOP2,	6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36	SOP,	SOP,	6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36
针数	36	32	36	36	32	36	32	32	36
Reach Compliance Code	unknown	unknow	unknow	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	70 ns	55 ns	70 ns	55 ns	70 ns	70 ns	70 ns	70 ns	70 ns
JESD-30 代码	R-PBGA-B36	R-PDSO-G32	R-PBGA-B36	R-PBGA-B36	R-PDSO-G32	R-PBGA-B36	R-PDSO-G32	R-PDSO-G32	R-PBGA-B36
JESD-609代码	e0	e4	e0	e1	e3	e1	e4	e4	e1
长度	8 mm	20.4465 mm	8 mm	8 mm	20.95 mm	8 mm	20.4465 mm	20.4465 mm	8 mm
内存密度	4194304 bit	4194304 bi	4194304 bi	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit
内存集成电路类型	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
内存宽度	8	8	8	8	8	8	8	8	8
功能数量	1	1	1	1	1	1	1	1	1
端子数量	36	32	36	36	32	36	32	32	36
字数	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words
字数代码	512000	512000	512000	512000	512000	512000	512000	512000	512000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
组织	512KX8	512KX8	512KX8	512KX8	512KX8	512KX8	512KX8	512KX8	512KX8
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	VFBGA	SOP	VFBGA	VFBGA	TSOP2	VFBGA	SOP	SOP	VFBGA
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	SMALL OUTLINE	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	SMALL OUTLINE, THIN PROFILE	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	SMALL OUTLINE	SMALL OUTLINE	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1 mm	2.997 mm	1 mm	1 mm	1.2 mm	1 mm	2.997 mm	2.997 mm	1 mm
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	2.2 V	2.2 V	2.2 V	2.2 V	2.2 V	2.2 V	2.2 V	2.2 V	2.2 V
标称供电电压 (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	TIN LEAD	NICKEL PALLADIUM GOLD	TIN LEAD	TIN SILVER COPPER	MATTE TIN	TIN SILVER COPPER	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	TIN SILVER COPPER
端子形式	BALL	GULL WING	BALL	BALL	GULL WING	BALL	GULL WING	GULL WING	BALL
端子节距	0.75 mm	1.27 mm	0.75 mm	0.75 mm	1.27 mm	0.75 mm	1.27 mm	1.27 mm	0.75 mm
端子位置	BOTTOM	DUAL	BOTTOM	BOTTOM	DUAL	BOTTOM	DUAL	DUAL	BOTTOM
宽度	6 mm	11.303 mm	6 mm	6 mm	10.16 mm	6 mm	11.303 mm	11.303 mm	6 mm
厂商名称	Cypress(赛普拉斯)	-	-	Cypress(赛普拉斯)	-	Cypress(赛普拉斯)	Cypress(赛普拉斯)	Cypress(赛普拉斯)	Cypress(赛普拉斯)
Base Number Matches	1	1	1	1	1	1	-	-	-

CY62148DV30L-70BVIT

CY62148DV30L-70BVIT概述

CY62148DV30L-70BVIT规格参数

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