CY28439
Clock Generator for Intel Grantsdale Chipset
Features
• Compliant to Intel CK410
• Supports Intel Prescott and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks (two selectable
between Fixed and Overclocking)
• 96 MHz differential dot clock
• 48 MHz USB clocks
• 33 MHz PCI clock
• Dial-A-Frequency
• Watchdog
• Two independent overclocking PLLs
• Low-voltage frequency select input
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
•
56-pin SSOP and TSSOP packages
CPU SRC
x2
x6
PCI
x9
REF DOT96
x2
x1
USB
x1
24-48M
x1
Block Diagram
Xin
Xout
Pin Configuration
VDD_RE
F
RE
F
14.318MHz
Crystal
PLL Reference
IREF
VDD_CPU
CPUT
CPUC
PLL1
CPU
FS_[E:A]
Divider
VDD_SRC
SRCT (PCI Ex)
SRCC (PCI Ex)
PLL2
SRC
Divider
VDD_SRC
PLL3
SATA
Divider
SRCT4_SATA
SRCC4_SATA
VDD_48Mhz
PLL4
Fixed
Divider
DOT96T
DOT96C
VDD_48
USB48
VDD_48
24/48
VDD_PCI
PCI
VDD_PCI
PCIF
VTTPWR_GD#/PD
VSS_PCI
PCI3
*FS_E/PCI4
PCI5
VSS_PCI
VDD_PCI
PCIF0
**FS_A/PCIF1
*FS_B/PCIF2
VDD_48
**SEL24_48#/24_48M
USB48
VSS_48
DOT96T
DOT96C
VTTPWRGD#/PD
SRCT0
SRCC0
VDD_SRC
VSS_SRC
SRCT1
SRCC1
SRCT2
SRCC2
VSS_SRC
SRCT_SATAT
SRCC_SATAC
VDD_SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_PCI
PCI2
PCI1
PCI0
SRESET#
REF1/FS_C**
REF0/FS_D**
VSS_REF
XIN
XOUT
VDD_REF
SCLK
SDATA
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
VSS_CPU
IREF
VSSA
VDDA
VDD_SRC
SRCT4
SRCC4
SRCT3
SRCC3
VSS_SRC
* Indicates internal pull-up
** Indicates internal pull-down
CY28439
SDATA
SCLK
I2C
Logic
Watchdog
Timer
SRESET#
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 21
www.SpectraLinear.com
CY28439
Pin Description
Pin No.
6,56
1,5
3
Name
VDD_PCI
VSS_PCI
FS_E/PCI4
Type
PWR
GND
3.3V power supply for outputs.
Ground for outputs.
Description
I,O,
3.3V-tolerant input for CPU frequency selection/33-MHz clock.
PU,SE Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
O, SE
33-MHz clocks.
O,SE
33-MHz free running clock
I/O,PD,
3.3V-tolerant input for CPU frequency selection/Free running 33-MHz clock.
SE
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
I/O, PU,
3.3V-tolerant input for CPU frequency selection/Free running 33-MHz clock.
SE
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
I, PD
3.3V LVTTL input.
This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C,FS_D, FS_E, SEL24_48. After VTT_PWRGD# (active LOW) assertion, this pin
becomes a real-time input for asserting power down (active HIGH).
3.3V power supply for outputs.
2,4,53,54, PCI
55
7
8
9
16
PCIF0
FS_A/PCIF1
FS_B/PCIF2
VTT_PWRGD#/PD
10
11
12
13
14,15
17,18,21,
22,23,24,
30,31,32,
33
19,28,34
26,27
20,25,29
35
36
37
41
38
45
44
46
47
48
49
50
51
VDD_48
PWR
SEL24_48#/24_48 I/O, PD,
Latched select input for 24-/48-MHz output/ 24-/48-MHz output
M
SE
0 = 48 MHz, 1 = 24 MHz
USB48
VSS_48
DOT96T, DOT96C
SRCT/C
I/O,
GND
48-MHz clock output.
Ground for outputs.
O, DIF
Fixed 96-MHz clock output.
O, DIF
Differential serial reference clocks.
Outputs have overclocking capability.
VDD_SRC
SRCT/C_SATAT/C
VSS_SRC
VDDA
VSSA
IREF
VDD_CPU
VSS_CPU
SCLK
SDATA
VDD_REF
XOUT
XIN
VSS_REF
REF0/FS_D
REF1/FS_C
PWR
GND
PWR
GND
I
PWR
GND
I
I/O
PWR
I
GND
3.3V power supply for outputs.
Ground for outputs.
3.3V power supply for PLL.
Ground for PLL.
A precision resistor is attached to this pin,
which is connected to the internal current
reference.
3.3V power supply for outputs.
Ground for outputs.
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
3.3V power supply for outputs.
14.318-MHz crystal input.
Ground for outputs.
O, DIF
Differential serial reference clock.
Recommended output for SATA.
39,40,42,43 CPUT/C
O, DIF
Differential CPU clock outputs.
O, SE
14.318-MHz crystal output.
I/O, SE,
3.3V-tolerant input for CPU frequency selection/Reference clock.
Refer to DC
PD Electrical Specifications table for Vil_FS and Vih_FS specifications.
O, SE,
3.3V-tolerant input for CPU frequency selection/Reference clock.
PD Selects test mode if pulled to V
IHFS_C
when VTT_PWRGD# is asserted low.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifica-
tions.
O, SE
3.3V output for Watchdog reset.
This output is open drain type with a high (>100-k ) internal pull-up resistor.
52
SRESET#
Rev 1.0, November 21, 2006
Page 2 of 21
CY28439
Frequency Select Pins (FS_[A:E])
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C, FS_D, and
FS_E inputs prior to VTT_PWRGD# assertion (as seen by the
clock synthesizer). Upon VTT_PWRGD# being sampled LOW
by the clock chip (indicating processor VTT voltage is stable),
the clock chip samples the FS_A, FS_B, FS_C, FS_D, and
FS_E input values. For all logic levels of FS_A, FS_B, FS_C,
FS_D, and FS_E, VTT_PWRGD# employs a one-shot
functionality in that once a valid LOW on VTT_PWRGD# has
been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C,
FS_D, and FS_E transitions will be ignored, except in test
mode. FS_C is a three level input, when sampled at a voltage
greater than 2.1V by VTTPWRGD#, the device will enter test
mode as selected by the voltage level on the FS_B input.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
Input Conditions
FS_D
FS_C
FS_B
FS_A
Output Frequency
CPU
SRC
SRC M
CPU PLL CPU M CPU N CPU N SRC PLL
SRC N
SRC N
divider (not DEFAULT allowable
Gear
divider DEFA
ULT allowable
Gear
Constants
range for Constants changeable
range for
by user)
DAF
DAF
(G)
FSEL_3
FSEL_2
FSEL_1
FSEL_0
(MHz)
(MHz)
0
0
0
0
0
0
0
1
1
1
1
1
1
1
X
X
1
0
0
0
0
1
1
1
0
0
0
0
1
1
HIGH
HIGH
0
0
1
1
0
0
1
0
0
1
1
0
0
1
LOW
HIGH
1
1
1
0
0
0
0
1
1
1
0
0
0
0
X
X
100
133.3333333
166.6666667
200
266.6666667
333.3333333
400
100.952381
133.968254
167
200.952381
266.6666667
334
400.6451613
Tristate
REF/N
100
100
100
100
100
100
100
100
100
100
100
100
100
100
Tristate
REF/N
30
40
60
60
80
120
120
30
40
60
60
80
120
120
Tristate
REF/N
60
60
63
60
60
63
60
63
63
60
63
60
60
62
Tristate
REF/N
200
200
175
200
200
175
200
212
211
167
211
200
167
207
Tristate
REF/N
200 - 250
200 - 250
175 - 262
200 - 250
200 - 250
175 - 262
200 - 250
212 - 262
211 - 262
167 - 250
211 - 262
200 - 250
167 - 250
207 - 258
Tristate
REF/N
30
30
30
30
30
30
30
30
30
30
30
30
30
30
60
60
60
60
60
60
60
60
60
60
60
60
60
60
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 167 - 266
200 167 - 266
Figure 1. CPU and SRC Frequency Select Tables
Rev 1.0, November 21, 2006
Page 3 of 21
CY28439
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
Rev 1.0, November 21, 2006
Page 4 of 21
CY28439
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
RESERVED
SRC[T/C]4
SRC[T/C]3
SATA[T/C]
SRC[T/C]2
SRC[T/C]1
RESERVED
SRC[T/C]0
RESERVED
SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SATA[T/C] Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
RESERVED
SRC[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enable
Description
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
0
1
1
1
Name
PCIF0
DOT_96[T/C]
24_48M
REF0
RESERVED
CPU[T/C]1
CPU[T/C]0
CPU
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
24_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
RESERVED
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Description
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
@Pup
1
1
1
1
1
1
1
Name
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
PCIF2
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
Description
Rev 1.0, November 21, 2006
Page 5 of 21
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