Freescale Semiconductor, Inc.
MC68HC11G5/D
MC68HC11G5
Freescale Semiconductor, Inc...
HC11
MC68HC11G5
MC68HC11G7
MC68HC711G5
TECHNICAL
DATA
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TECHNICAL DATA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MC68HC11G5
MC68HC11G7
MC68HC711G5
High-density Complementary Metal Oxide
Semiconductor (HCMOS) Microcontroller
Unit
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Freescale Semiconductor, Inc.
TABLE OF CONTENTS (Continued)
Paragraph
Number
Page
Number
Title
TABLE OF CONTENTS
Paragraph
Number
Page
Number
Freescale Semiconductor, Inc...
Title
Section 1
Introduction
1.1
1.2
General ........................................................................................................
Features of the
Freescale
MC68HC11G5 MCU ............................................
1-1
1-1
Section 2
Operating Modes and Signal Description
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.4.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10
2.2.11
Operating Modes .........................................................................................
Single Chip Operating Mode ..................................................................
Expanded Non-Multiplexed Operating Mode .........................................
Bootstrap Operating Mode .....................................................................
Test Operating Mode ..............................................................................
Factory Test Register (TEST1) .........................................................
Signal Description ........................................................................................
Input Power (VDD) and Ground (VSS) ...................................................
Reset (RESET) .......................................................................................
Crystal Driver (XTAL) and External Clock Input (EXTAL) ......................
E-clock Output (E) ..................................................................................
Read/Write (R/W) ...................................................................................
Interrupt Request (IRQ) ..........................................................................
Non-Maskable Interrupt (XIRQ) ..............................................................
Halt (HALT) ............................................................................................
Mode A/Load Instruction Register (MODA/LIR) and Mode B/Standby
Voltage (MODB/Vkam) ...........................................................................
A/D Converter Reference Voltages (Vrl, Vrh) .........................................
Port Signals ............................................................................................
2-1
2-2
2-2
2-2
2-2
2-4
2-5
2-5
2-6
2-7
2-7
2-7
2-7
2-7
2-7
2-8
2-8
2-8
i
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TABLE OF CONTENTS (Continued)
Paragraph
Number
Page
Number
Title
Section 3
Memory and Control/Status Registers
Freescale Semiconductor, Inc...
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.5
3.5.1
3.5.2
3.6
ROM .............................................................................................................
Bootstrap ROM ............................................................................................
RAM .............................................................................................................
Memory Map ................................................................................................
Single Chip Mode ...................................................................................
Expanded Non-multiplexed Mode ..........................................................
Special Bootstrap Mode .........................................................................
Special Test Mode ..................................................................................
Changing Modes ....................................................................................
System Configuration ...................................................................................
RAM and I/O Mapping Register (INIT) ...................................................
Configuration Control Register (CONFIG) ..............................................
Control/Status Registers ..............................................................................
3-1
3-1
3-1
3-2
3-2
3-3
3-4
3-4
3-4
3-4
3-5
3-6
3-6
Section 4
Input/Output Ports
4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.5
4.5.1
4.6
4.6.1
4.6.2
4.7
4.7.1
4.7.2
4.8
4.8.1
4.9
4.9.1
Mode Dependencies ....................................................................................
General Purpose I/O (Ports A, C, D, G, H, and J) .......................................
Fixed Direction I/O (Ports B, E, and F) ........................................................
Port A ...........................................................................................................
Data Register (PORTA ) .........................................................................
Data Direction Register (DDRA ) ............................................................
Port B ...........................................................................................................
Data Register (PORTB) ..........................................................................
Port C ...........................................................................................................
Data Register (PORTC) .........................................................................
Data Direction Register (DDRC) ............................................................
Port D ...........................................................................................................
Data Register (PORTD) .........................................................................
Data Direction Register (DDRD) ............................................................
Port E ...........................................................................................................
Data Register (PORTE) ..........................................................................
Port F ...........................................................................................................
Data Register (PORTF) ..........................................................................
4-1
4-2
4-2
4-2
4-3
4-3
4-4
4-4
4-4
4-5
4-5
4-5
4-6
4-6
4-7
4-7
4-8
4-8
ii
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TABLE OF CONTENTS (Continued)
Paragraph
Number
Page
Number
Title
Freescale Semiconductor, Inc...
4.10
4.10.1
4.10.2
4.11
4.11.1
4.11.2
4.12
4.12.1
4.12.2
4.13
4.13.1
4.13.2
4.13.3
Port G ...........................................................................................................
Data Register (PORTG) .........................................................................
Data Direction Register (DDRG) ............................................................
Port H ...........................................................................................................
Data Register (PORTH) .........................................................................
Data Direction Register (DDRH) ............................................................
Port J ............................................................................................................
Data Register (PORTJ) .........................................................................
Data Direction Register (DDRJ) ............................................................
Expanded Bus (Ports B, C, F) ......................................................................
R/W ........................................................................................................
Memory Ready (MRDY) .........................................................................
Options Register 2 (OPT2) .....................................................................
4-8
4-9
4-9
4-9
4-10
4-10
4-11
4-11
4-11
4-12
4-12
4-13
4-13
Section 5
Resets, Interrupts and Low Power Modes
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.3
5.3.1
5.3.2
Resets ..........................................................................................................
RESET Pin .............................................................................................
Power-on-reset (POR) ............................................................................
Computer Operating Properly (COP) Reset ...........................................
Clock Monitor Reset ...............................................................................
Configuration Options Register (OPTION) .............................................
State After Reset ....................................................................................
Interrupts ......................................................................................................
Interrupt Vector Assignments .................................................................
Software Interrupt (SWI) .........................................................................
Illegal Opcode Trap ................................................................................
Real Time Interrupt .................................................................................
Interrupt Mask Bits in Condition Code Register .....................................
Priority and Masking Structure ...............................................................
“Highest Priority I” Interrupt and Miscellaneous Register (HPRIO) ........
Low Power Modes .......................................................................................
WAIT ......................................................................................................
STOP ......................................................................................................
5-1
5-1
5-1
5-2
5-2
5-3
5-4
5-6
5-6
5-8
5-8
5-8
5-9
5-9
5-15
5-17
5-17
5-17
iii
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