FemtoClock
®
Crystal-to-HCSL
Clock Generator
General Description
The ICS841664I is an optimized sRIO clock generator and a
member of the family of high-performance clock solutions from IDT.
The device uses a 25MHz parallel crystal to generate 125MHz and
156.25MHz clock signals, replacing solution requiring multiple
oscillator and fanout buffer solutions. The device has excellent phase
jitter (<1ps RMS) suitable to clock components requiring precise and
low-jitter sRIO clock signals. Designed for telecom, networking and
industrial application, the ICS841664I can also drive the high-speed
sRIO SerDes clock inputs of communication processors, DSPs,
switches and bridges.
ICS841664I
DATA SHEET
Features
•
Four differential HCSL clock outputs: configurable for sRIO
(125MHz or 156.25MHz) clock signals
One REF_OUT LVCMOS/LVTTL clock output
Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference clock
input or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 125MHz or 156.25MHz
VCO: 625MHz
Supports PLL bypass and output enable functions
RMS phase jitter, using a 25MHz crystal (1.875MHz - 20MHz):
0.45ps (typical) @ 125MHz
Full 3.3V power supply mode
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
•
•
•
•
•
•
•
•
Block Diagram
Pin Assignment
V
DD
REF_OUT
GND
QA0
nQA0
V
DDOA
GND
QA1
nQA1
nREF_OE
BYPASS
REF_IN
REF_ SEL
V
DDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IREF
FSEL0
FSEL1
QB0
nQB0
V
DDOB
GND
QB1
nQB1
MR/nOE
V
DD
XTAL _IN
XTAL_OUT
GND
XTAL_IN
25MHz
XTAL_OUT
REF_IN
REF_SEL
IREF
OSC
0
fref
1
QA0
nQA0
FemtoClock
PLL
VCO = 625MHz
0
÷ NA
Pulldown
1
QA1
nQA1
Pulldown
M = ÷25
QB0
nQB0
÷ NB
BYPASS
Pulldown
Pulldown
Pulldown
QB1
nQB1
FSEL[0:1]
MR/nOE
REF_OUT
nREF_OE
Pullup
ICS841664I
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
G Package
Top View
ICS841664AGI REVISION A JULY 15, 2013
1
©2013 Integrated Device Technology, Inc.
ICS841664I Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-HCSL CLOCK GENERATOR
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 18
2
3, 7, 15, 22
4, 5,
8, 9
6
10
11
12
13
14
16,
17
Name
V
DD
REF_OUT
GND
QA0, nQA0
QA1, nQA1
V
DDOA
nREF_OE
BYPASS
REF_IN
REF_SEL
V
DDA
XTAL_OUT,
XTAL_IN
Power
Output
Power
Output
Power
Input
Input
Input
Input
Power
Input
Pullup
Pulldown
Pulldown
Pulldown
Type
Description
Core supply pins.
LVCMOS/LVTTL reference frequency clock output.
Power supply ground.
Differential Bank A output pairs. HCSL interface levels.
Output supply pin for Bank A outputs.
Active low REF_OUT enable/disable. See Table 3E.
LVCMOS/LVTTL interface levels.
Selects PLL/PLL bypass mode. See Table 3C. LVCMOS/LVTTL interface levels.
LVCMOS/LVTTL reference clock input.
Reference select, Selects the input reference source. See Table 3B.
LVCMOS/LVTTL interface levels
Analog supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the outputs are in high impedance. When logic
LOW, the internal dividers and the outputs are enabled. See Table 3D.
LVCMOS/LVTTL interface levels.
Differential Bank B output pairs. HCSL interface levels.
Output supply pin for Bank B outputs.
Pulldown
Output frequency select pins. LVCMOS/LVTTL interface levels.
HCSL current reference resistor output. A fixed precision resistor (475
) form this
pin to ground provides a reference current used for differential current-mode
QX[0:1], nQX[0:1] clock outputs.
19
MR/nOE
Input
Pulldown
20, 21,
24, 25
23
26,
27
28
nQB1, QB1
nQB0, QB0
V
DDOB
FSEL1,
FSEL0
IREF
Output
Power
Input
Output
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
REF_OUT
V
DD
= 3.465V
V
DD
= 3.465V
Test Conditions
Minimum
Typical
4
4
51
51
20
Maximum
Units
pF
pF
k
k
ICS841664AGI REVISION A JULY 15, 2013
2
©2013 Integrated Device Technology, Inc.
ICS841664I Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-HCSL CLOCK GENERATOR
Function Tables
Table 3A. NA, NB FSELx Function Table (f
ref
= 25MHz)
Inputs
FSEL1
0
0
1
1
FSEL0
0
1
0
1
M
25
25
25
25
Outputs Frequency Settings
QA[0:1], nQA[0:1]
VCO/5 (125MHz)
VCO/5 (125MHz)
VCO/5 (125MHz)
VCO/4 (156.25MHz)
QB[0:1], nQB[0:1]
VCO/5 (125MHz)
VCO/4 (156.25MHz)
QB0:1 = L, nQB0:1 = H
VCO/4 (156.25MHz)
Table 3B. REF_SEL Function Table
Input
REF_SEL
0
1
Input Reference
XTAL
REF_IN
Table 3C. BYPASS Function Table
Input
BYPASS
0
1
PLL Configuration
NOTE 1
PLL enabled
PLL bypassed (QA, QB = fref/Nx, x = A or B)
NOTE 1: Asynchronous control.
Table 3D. MR/nOE Function Table
Input
MR/nOE
0
1
Function
NOTE 1
Outputs enabled
Internal dividers reset, outputs disabled (High impedance)
NOTE 1: Asynchronous control.
Table 3E. nREF_OE Function Table
Input
nREF_OE
0
1
Function
NOTE 1
REF_OUT enabled
REF_OUT disabled (high impedance)
NOTE 1: Asynchronous control.
ICS841664AGI REVISION A JULY 15, 2013
3
©2013 Integrated Device Technology, Inc.
ICS841664I Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-HCSL CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs,I
O
Continuous Current REF_OUT
Surge Current REF_OUT
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
15mA
30mA
64.5C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDOA
= V
DDOB
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDOA,
V
DDOB
I
DD
I
DDA
I
DDOA,
I
DDOB
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
No Load
No Load, R
REF
= 475%
Test Conditions
Minimum
3.135
V
DD
– 0.20
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
80
20
5
Units
V
V
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL0, FSEL1
nREF_OE
REF_IN, REF_SEL,
BYPASS, MR/nOE,
FSEL0, FSEL1
nREF_OE
V
OH
V
OL
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
REF_OUT
REF_OUT
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V
V
DD
= 3.465V
-5
-150
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
V
V
I
IH
Input High Current
I
IL
Input Low Current
NOTE 1: Outputs termination with 50
to V
DD
/2. See Parameter Measurement Information Section,
Output Load Test Circuit diagram.
ICS841664AGI REVISION A JULY 15, 2013
4
©2013 Integrated Device Technology, Inc.
ICS841664I Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-HCSL CLOCK GENERATOR
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Maximum
Units
pF
AC Electrical Characteristics
Table 6A. LVCMOS AC Characteristics,
V
DD
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
t
R
/ t
F
odc
Parameter
Output Frequency REF_OUT
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
1.5
47
Test Conditions
Minimum
Typical
25
2.2
53
Maximum
Units
MHz
ns
%
ICS841664AGI REVISION A JULY 15, 2013
5
©2013 Integrated Device Technology, Inc.
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