VCXO-TO-LVCMOS/LVTTL OUTPUT
ICS810525I
G
ENERAL
D
ESCRIPTION
The ICS810525I is a high performance, low jit-
t e r / l o w p h a s e n o i s e V C X O f r o m I D T. T h e
HiPerClockS™
ICS810525I works in conjunction with a 25MHz
pullable crystal to generate an LVCMOS/LVTTL
output clock of 25MHz from an input clock of
5MHz. The frequency of the VCXO is adjusted by the VC
control voltage input. The output range is ±100ppm around
the nominal crystal frequency. The LF1 control voltage range
is 0 – V
DD
. The device is packaged in a small 16 TSSOP
package and is ideal for use on space constrained boards.
F
EATURES
•
One single-ended LVCMOS/LVTTL output
•
One single-ended clock accepts the following input types:
LVCMOS, LVTTL
•
Accepts input frequency of 5MHz
•
Absolute pull range: 100ppm
•
Proprietary multiplier provides low jitter, high frequency output
•
RMS phase jitter @ 25MHz, using a 25MHz crystal
(1kHz – 1MHz): 0.27ps (typical)
•
Full 3.3V supply, or 3.3V core/2.5V output supply
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
IC
S
B
LOCK
D
IAGRAM
XTAL_OUT
(External
Loop Filter Inputs)
P
IN
A
SSIGNMENT
nc
GND
Q
V
DDO
nc
nc
V
DDA
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
CLK
GND
LF1
LF0
XTAL_IN
XTAL_OUT
GND
XTAL_IN
25MHz
LF0 LF1
ICS810525I
CLK
Pulldown
5MHz
x5 VCXO
PLL
Q
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
IDT
™
/ ICS
™
VCXO-TO-LVCMOS/LVTTL OUTPUT
1
ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 5, 6
2, 9, 14
3
4
7
8, 16
10,
11
12, 13
15
Name
nc
GND
Q
V
DDO
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
LF0, LF1
CLK
Power
Output
Power
Power
Power
Input
Analog
Input/Output
Input
Type
Unused
Description
No connect.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output power supply pin.
Analog supply pin.
Core power supply pins.
VCXO crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Loop filter connection node pins.
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pulldown Resistor
Output Impedance
V
DDO
= 3.3V
V
DDO
= 2.5V
V
DDO
= 3.465V
V
DDO
= 2.625V
Test Conditions
Minimum
Typical
4
8
5
51
15
20
Maximum
Units
pF
pF
pF
kΩ
Ω
Ω
IDT
™
/ ICS
™
VCXO-TO-LVCMOS/LVTTL OUTPUT
2
ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
92.4°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
Parameter
Power Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.05
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
35
5
Units
V
V
V
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
DD
V
DDA
V
DDO
I
DD
I
DDA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.05
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
V
DD
2.625
35
5
Units
V
V
V
mA
mA
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
V
LF1
I
IH
I
IL
I
I
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
VCXO Control Voltage
Input High Current
Input Low Current
Input Current of V
LF1
pin
Output High Voltage
Output Low Voltage
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V
V
DDO
= 3.3V ± 5%, I
OH
= -12mA
V
DDO
= 2.5V ± 5%, I
OH
= -12mA
V
DDO
= 3.3V or 2.5V ± 5% I
OL
= 12mA
-5
-100
2.6
1.8
0.5
100
Test Conditions
Minimum
2
-0.3
0
Typical
Maximum
V
DD
+ 0.3
0.8
V
DD
150
Units
V
V
V
µA
µA
µA
V
V
V
IDT
™
/ ICS
™
VCXO-TO-LVCMOS/LVTTL OUTPUT
3
ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Output Rise/Fall Time
Test Conditions
Integration Range:
1kHz – 1MHz
20% to 80%
Minimum
Typical
Maximum
25
0.27
500
1200
Units
MHz
ps
ps
t
jit(Ø)
t
R
/ t
F
odc
Output Duty Cycle
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
Characterized using a 3kHz bandwidth filter.
NOTE 1: Please refer to the Phase Noise Plot.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Output Rise/Fall Time
Test Conditions
Integration Range:
1kHz – 1MHz
20% to 80%
Minimum
Typical
Maximum
25
0.26
600
2100
Units
MHz
ps
ps
t
jit(Ø)
t
R
/ t
F
odc
Output Duty Cycle
44
56
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
Characterized using a 3kHz bandwidth filter.
NOTE 1: Please refer to the Phase Noise Plot.
IDT
™
/ ICS
™
VCXO-TO-LVCMOS/LVTTL OUTPUT
4
ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
➤
T
YPICAL
P
HASE
N
OISE AT
25MH
Z
@ 3.3V/3.3V
25MHz
Filter
RMS Phase Jitter (Random)
1kHz to 1MHz = 0.27ps (typical)
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
➤
Phase Noise Result by adding
a Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
➤
T
YPICAL
P
HASE
N
OISE AT
25MH
Z
@ 3.3V/2.5V
25MHz
Filter
RMS Phase Jitter (Random)
1kHz to 1MHz = 0.26ps (typical)
N
OISE
P
OWER
dBc
Hz
➤
Phase Noise Result by adding
a Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
IDT
™
/ ICS
™
VCXO-TO-LVCMOS/LVTTL OUTPUT
5
➤
Raw Phase Noise Data
➤
ICS810525AGI REV. B FEBRUARY 24, 2009
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