HANBit
HSD64M72D18RP
Synchronous DRAM Module 512Mbyte (64Mx72bit), DIMM with PLL & Register
based on 64Mx4, 4Banks, 8K Ref., 3.3V
GENERAL DESCRIPTION
The HSD64M72D18RP is a 64M x 72 bit Synchronous Dynamic RAM high-density memory module. The module consists
of eighteen CMOS 64M x 4 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin
TSSOP package on a 168-pin glass-epoxy 0.1uF decoupling capacitors are mounted on the printed circuit board in
parallel for each SDRAM. The HSD64M72D18RP is a DIMM (Dual in line Memory Module) and is intended for mounting
into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O
transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high performance memory system applications All module components
may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
Part No. HSD64M72D18RP
FEATURES
•
Part Identification
HSD64M72D18RP-10L : 100MHz (CL=3)
HSD64M72D18RP-10 : 100MHz (CL=2)
HSD64M72D18RP-13 : 133MHz (CL=3)
•
Burst mode operation
•
Auto & self refresh capability (8192 Cycles/64ms)
•
LVTTL compatible inputs and outputs
•
Single 3.3V
±0.3V
power supply
•
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
•
All inputs are sampled at the positive going edge of the system cloc
•
serial presence detect with EEPROM
•
The used device is 16M x 4bit x 4Banks SDRAM
URL:www.hbe.co.kr
REV.1.0 (August.2002)
1
HANBit Electronics Co.,Ltd.
HANBit
PIN ASSIGNMENT
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
Vss
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
CB0
CB1
V
CC
NC
NC
V
CC
/WE
DQM0
PIN
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Symbol
DQM1
/CS0
NC
Vss
A0
A2
A4
A6
A8
A10
BA1
V
CC
V
CC
CLK0
Vss
NC
/CS2
DQM2
DQM3
NC
V
CC
NC
NC
CB2
CB3
Vss
DQ16
DQ17
PIN
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
DQ18
DQ19
VDD
DQ20
NC
NC(*V
REF
)
*CKE1
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
Vss
*CLK2
NC
WP
**SDA
**SCL
V
CC
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Symbol
Vss
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
CB4
CB5
Vss
NC
NC
V
CC
/CAS
DQM4
PIN
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
HSD64M72D18RP
Symbol
DQM5
*/CS1
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
V
CC
*CLK1
A12
Vss
CKE0
*/CS3
DQM6
DQM7
*A13
V
CC
NC
NC
CB6
CB7
Vss
DQ48
DQ49
PIN
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
DQ50
DQ51
V
CC
DQ52
NC
NC(*V
REF
)
REGE
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
Vss
*CLK3
NC
**SA0
**SA1
**SA2
V
CC
* These pins are not used in this module
*Pin Names
A0~A12: Address input (Multiplexed)
DQ0~DQ63: Data input/output
CLK0~CLK3: Clock input
/CS0~/CS3: Chip select input
/CAS: Coulmn address strobe
DQM0~7: DQM
V
SS
: Ground
REGE: Register enable
SCL: Serial clock
WP: Write protection
NC: No connection
** These pins should be NC in the system which does not support SPD
BA0~BA1: Select bank
CB0~7: Check bit (Data-in/data-out)
CKE0~ CKE1: Clock enable input
/RAS: Row address strobe
/WE: Write enable
V
CC
: Power supply(3.3V)
*V
REF
:Power supply for reference
SDA: Serial data I/O
SA0~2: Address in EEPROM
URL:www.hbe.co.kr
REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd.
HANBit
FUNCTIONAL BLOCK DIAGRAM
HSD64M72D18RP
URL:www.hbe.co.kr
REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd.
HANBit
PIN FUNCTION DESCRIPTION
Pin
CLK
/CS
Name
System clock
Chip select
Input Function
HSD64M72D18RP
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9,CA11
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with /RAS low.
Enables row access & precharge.
/CAS
Column
strobe
address
Latches column addresses on the positive going edge of the CLK with /CAS low.
Enables column access.
/WE
Write
enable
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
DQM0 ~ 7
Data
mask
input/output
Makes data output Hi-Z, tsHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
The device operates in the transparent mode when REGE is low. When REGE is
high, the
device operates in the registered mode. In registered mode, the Address and
control inputs are latched if CLK is held at a high or low logic level. The inputs are
strobed in the latch/flip-flop on the riging edge of CLK. REGE is tied to V
DD
through 10K ohm register on PCB. So if REGE of module is floating, this module
will be operated as registerd mode.
REGE
Register enable
DQ0 ~ 63
CB0~7
WP
Data input/output
Check bit
Write Protection
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
WP pin is connected to Vcc.
When WP is
“high”,
EEPROM Programming will be inhibited and the entire
memory will be write-protected.
Vcc /V
SS
Power
supply/ground
Power and ground for the input buffers and the core logic.
URL:www.hbe.co.kr
REV.1.0 (August.2002)
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HANBit Electronics Co.,Ltd.
HANBit
ABSOLUTE MAXIMUM RATINGS
HSD64M72D18RP
PARAMETER
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
Storage Temperature
SYMBOL
V
IN ,OUT
Vcc
P
D
T
STG
RATING
-1V to 4.6V
-1V to 4.6V
18W
-55oC to 150oC
Short Circuit Output Current
I
OS
50mA
Notes:
Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, T
A
= 0 to 70°C) )
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
SYMBOL
Vcc
V
IH
V
IL
V
OH
V
OL
MIN
3.0
2.0
-0.3
2.4
-
TYP.
3.3
3.0
0
-
-
MAX
3.6
Vcc+0.3
0.8
-
0.4
UNIT
V
V
V
V
V
1
2
I
OH
= -2mA
I
OL
= 2mA
3
NOTE
Input leakage current
I
LI
-10
-
10
uA
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
CC
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(Vcc = 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=1.4V
±
200 mV)
DESCRIPTION
Input capacitance(A0~A12)
Input capacitance(/RAS, /CAS,/WE)
Input capacitance(CKE0)
Input capacitance(CLK0)
Input capacitance(/CS0~/CS3)
Input capacitance(DQM0~DQM7)
Input capacitance(BA0~BA1)
Data input/output capacitance (DQ0 ~ DQ63)
Data input/output capacitance (CB0 ~ CB7)
URL:www.hbe.co.kr
REV.1.0 (August.2002)
SYMBOL
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN3
C
IN3
C
OUT
C
OUT1
MIN
MAX
15
15
20
15
15
15
15
16
16
UNITS
pF
pF
pF
pF
pF
pF
pF
pF
pF
HANBit Electronics Co.,Ltd.
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