IS61NLP204836B/IS61NVP/NVVP204836B
IS61NLP409618B/IS61NVP/NVVP409618B
2M x 36 and 4M x 18
72Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control us-
ing MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
•
CKE
pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 119-
ball PBGA packages
• Power supply:
NLP: V
dd
3.3V (± 5%), V
ddq
3.3V/2.5V (± 5%)
NVP: V
dd
2.5V (± 5%), V
ddq
2.5V (± 5%)
NVVP: V
dd
1.8V (± 5%), V
ddq
1.8V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
ADVANCED INFORMATION
FEBRUARY 2013
DESCRIPTION
The 72 Meg product family features high-speed, low-power
synchronous static RAMs designed to provide a burstable,
high-performance, 'no wait' state, device for networking
and communications applications. They are organized as
2,096,952 words by 36 bits and 4,193,904 words by 18
bits, fabricated with
ISSI
's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable,
CKE
is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock inputs and when
WE
is
LOW. Separate byte enables allow individual bytes to be
written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
t
kq
t
kc
Parameter
Clock Access Time
Cycle Time
Frequency
-250
2.6
4
250
-200
3.1
5
200
166
3.5
6
166
Units
ns
ns
MHz
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00C
02/20/2013
1
IS61NLP204836B/IS61NVP/NVVP204836B
IS61NLP409618B/IS61NVP/NVVP409618B
PIN CONFIGURATION — 2M
x
36, 165-Ball PBGA (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
A
A
3
CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
4
BWc
BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
BWb
BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1*
A0*
7
CKE
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
ADV
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
A
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
Pin Name
Synchronous Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Synchronous Clock Enable
CE, CE2,
CE2 Synchronous Chip Enable
BWa-BWd
Synchronous Byte Write Inputs
OE
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
MODE
TCK, TDI
TDO, TMS
V
DD
NC
DQa-DQd
DQPa-DQPd
V
DDQ
V
ss
Burst Sequence Selection
JTAG Pins
Power Supply
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data
Inputs/Outputs
I/O Power Supply
Ground
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
ARM技术
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