HYM7V64200C Z-Series
SO-DIMM 2Mx64 bit SDRAM Module
based on 2Mx8 SDRAM, LVTTL, 4K-Refresh
DESCRIPTION
The HYM7V64200C is high speed 3.3Volt CMOS Synchronous DRAM module consisting of eight 2Mx8 bit
Synchronous DRAMs in 44-pin TSOPII and one 8-pin TSSOP 2K bit EEPROM on a 168-pin glass-epoxy
circuit board. One 0.33µF and one 0.1µF decoupling capacitors are mounted for each SDRAM.
The HYM7V64200C is a gold plated socket type Dual In-line Memory Module suitable for easy interchange
and addition of 16M byte memory. All inputs and outputs are synchronized with the rising edge of the clock
input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage
levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of
consecutive read of write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page),
and the burst count sequence(sequential or interleave). A burst of read of write cycles in progress can be
terminated by a burst terminate command of can be interrupted and replaced by a new burst read or write
command on any cycle. (This pipelined design is not restricted by a ‘ 2N’ rule.)
FEATURES
•
•
•
•
•
•
144Pin SO-DIMM, JEDEC Standard
Serial Presence Detect with EEPROM
Single 3.3V±0.3V power supply
All module pins are LVTTL compatible
4096 refresh cycles / 64ms
All inputs and outputs referenced to positive
edge of system clock
•
Auto refresh and Self Refresh
•
Programmable burst lengths and sequences
- 1,2,4,8 and full page for Sequential type
- 1,2,4 and 8 for Interleave type
•
Programmable /CAS latency ; 1,2,3 clocks
ORDERING INFORMATION
Part No.
HYM7V64200CLTZG -8
HYM7V64200CLTZG -10P
HYM7V64200CLTZG -10S
HYM7V64200CLTZG -10
Max.
Frequency
125MHz
100MHz
100MHz
100MHz
Power
L-Part
L-Part
L-Part
L-Part
PCB
height
1.00
1.00
1.00
1.00
Package
TSOPII
TSOPII
TSOPII
TSOPII
Based Comp. Part No
HY57V161610CLTC-8
HY57V161610CLTC-10P
HY57V161610CLTC-10S
HY57V161610CLTC-10
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.5 / MAY. 98
1998 Hyundai Semiconductor
HYM7V64200C Z-Series
PIN DESCRIPTION
Pin
CK0, CK1
Clock
Pin Name
Description
System Clock Input; All other inputs are referenced to the
SDRAM on the rising edge of CLK.
Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among power down, suspend,
or self refresh.
Select either one of dual banks during both /RAS and /CAS
activity.
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Command input enable or mask except CLK, CKE and DQM
CKE0
Clock Enable
BA0
Bank Address
A0-A10
/S0
Address
Chip Select
Row Address
Strobe,Column Address
Strobe, Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Write Protection
Serial Presence Detect
Data
Serial Presence Detect
Clock
Serial Presence Detect
Address
/RAS, /CAS,
/WE
DQMB0-7
DQ0-DQ63
V
CC
/ V
SS
WP
SDA
SCL
SA0-SA2
/RAS, /CAS and /WE define the operation.
DQM control output buffer in read mode and mask input data
in write mode
Multiplexed data input / output pin
Power supply for internal circuit and input buffer
EEPROM Write Protection
EEPROM Serial Presence Detect Data Input / Output pin
EEPROM Serial Presence Detect Clock input
EEPROM Serial Presence Detect Address input
Rev. 0.5
2
HYM7V64200C Z-Series
PIN NAME
#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NAME
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
DQMB0
DQMB1
Vcc
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ12
DQ13
DQ14
DQ15
Vss
NC
NC
CK0
Vcc
/RAS
/WE
/S0
NC
#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
NAME
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
DQMB4
DQMB5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
DQ45
DQ46
DQ47
Vss
NC
NC
CKE0
Vcc
/CAS
NC
NC
NC
#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
NAME
DU
Vss
NC
NC
Vcc
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10(AP)
Vcc
DQMB2
DQMB3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
#
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
NAME
CK1
Vss
NC
NC
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
DQ54
DQ55
Vcc
A7
BA0
Vss
NC
NC
Vcc
DQMB6
DQMB7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
3
Rev. 0.5
HYM7V64200C Z-Series
BLOCK DIAGRAM
Note
: 1. The serial resistor values of DQs are 10 Ohms.
Rev. 0.5
4
HYM7V64200C Z-Series
SERIAL PRESENCE DETECT
BYTE NUMBER
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
FUNCTION DESCRIBED
# of Byte Written into Serial Memory
at Module Manufacturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly(Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @ /CAS Latency=3
8 part
10P part
10S part
10 part
SDRAM Access Time from Clock @ /CAS Latency=3
8 part
10P part
10S part
10 part
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back
Random Column Address
Burst Lengths Supported
# of Banks on SDRAM Device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
( Non Buffered and Registered )
SDRAM Module Attributes General
( Burst read, Single bit write, Precharge All, Auto Precharge )
SDRAM Cycle Time @ /CAS Latency=2
8 part
10P part
10S part
10 part
SDRAM Access Time from Clock @ /CAS Latency=2
8 part
10P part
10S part
10 part
FUNCTION
128 Bytes
256 Bytes
SDRAM
11
9
1 Bank
64 Bits
-
LVTTL
8ns
10ns
10ns
10ns
6ns
6ns
6ns
8ns
None
15.625µs
/ Self Refresh Supported
x8
None
tCCD=1 CLK
1,2,4,8,Full Page
2 Banks
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
-
VALUE
80h
08h
04h
0Bh
09h
01h
40h
00h
01h
80h
A0h
A0h
A0h
60h
60h
60h
80h
00h
80h
08h
00h
01h
8Fh
02h
06h
01h
01h
00h
0Eh
NOTE
1
1
BYTE10
BYTE11
BYTE12
BYTE13
BYTE14
BYTE15
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
BYTE22
BYTE23
10ns
10ns
12ns
10ns
6ns
6ns
6ns
8ns
A0h
A0h
C0h
A0h
60h
60h
60h
80h
BYTE24
Note:
1. The bank address is excluded.
5
Rev. 0.5
嵌入式系统
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