25
PRELIMINARY
CY7C1370AV25
CY7C1372AV25
512Kx36/1Mx18 Pipelined SRAM with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between write and
read cycles
• Fast clock speed: 167, 150, 133, and 100 MHz
• Fast access time: 3.4, 3.8, 4.2, 5.0 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 2.5V + 5%
• Single WE (READ/WRITE) control pin
• Positive clock-edge triggered, address, data, and con-
trol signal registers for fully pipelined applications
• Interleaved or linear 4-word burst capability
• Individual byte write (BWS
a
- BWS
d
) control (may be
tied LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• JTAG boundary scan
• Available in 119- ball bump BGA and 100-pin TQFP
packages
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE
1
, CE
2
and CE
3
), cycle start input (ADV/LD),
Clock Enable (CEN), Byte Write Selects (BWS
a
, BWS
b
, BWS
c
and BWS
d
), and read-write control (WE). BWS
c
and BWS
d
apply to CY7C1370AV25 only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data oc-
curs, either read or write.
A Clock Enable (CEN) pin allows operation of the
CY7C1370AV25/CY7C1372AV25 to be suspended as long as
necessary. All synchronous inputs are ignored when (CEN) is
high and the internal device registers will hold their previous
values.
There are three Chip Enable (CE
1
, CE
2
, CE
3
) pins that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is low, no new mem-
ory operation can be initiated and any burst cycle in progress
is stopped. However, any pending data transfers (read or write)
will be completed. The data bus will be in high impedance state
two cycles after chip is deselected or a write cycle is initiated.
The CY7C1370AV25 and CY7C1372AV25 have an on-chip 2-
bit burst counter. In the burst mode, the CY7C1370AV25 and
CY7C1372AV25 provide four cycles of data for a single ad-
dress presented to the SRAM. The order of the burst sequence
is defined by the MODE input pin. The MODE pin selects be-
tween linear and interleaved burst sequence. The ADV/LD sig-
nal is used to load a new external address (ADV/LD=LOW) or
increment the internal burst counter (ADV/LD=HIGH)
Output Enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the out-
puts at any given time. ZZ may be tied to LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Functional Description
The CY7C1370AV25 and CY7C1372AV25 SRAMs are de-
signed to eliminate dead cycles when transitions from READ
to WRITE or vice versa. These SRAMs are optimized for 100
percent bus utilization and achieves Zero Bus Latency. They
integrate 524,288x36 and 1,048,576x18 SRAM cells, respec-
tively, with advanced synchronous peripheral circuitry and a 2-
bit counter for internal burst operation. The Cypress Synchro-
nous Burst SRAM family employs high-speed, low-power
CMOS designs using advanced triple-layer polysilicon, dou-
ble-layer metal technology. Each memory cell consists of four
transistors and two high-valued resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE
2
CE
3
WE
BWS
x
Mode
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
OUTOUT
REGISTERS
and LOGIC
D
Data-In REG.
Q
DQ
x
DP
x
CY7C1370
A
X
DQ
X
DP
X
BWS
X
X = 18:0
X = a, b, c, d
X = a, b, c, d
X = a, b, c, d
CY7C1372
X = 19:0
X = a, b
X = a, b
X = a, b
OE
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 10, 2000
PRELIMINARY
Selection Guide
7C1370A-167
7C1372A-167
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain advance information.
CY7C1370AV25
CY7C1372AV25
7C1370A-150
7C1372A-150
3.8
310
30
7C1370A-133
7C1372A-133
4.2
280
30
7C1370A-100
7C1372A-100
5.0
250
30
3.4
Com’l
350
30
Pin Configurations
100-Pin TQFP Packages
A
A
CE
1
CE
2
BWSd
BWSc
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
CE
1
CE
2
NC
NC
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
A
A
DPb
DQb
DQb
V
DDQ
V
SS
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DPc
DQc
DQc
V
DDQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
V
DD
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1370AV25
(512K x 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
V
DD
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DPb
NC
V
SS
V
DDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQb
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
SS
V
DD
V
DD
NC
DQa
DQa
V
DDQ
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
DPa
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
V
DD
V
DD
NC
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
CY7C1372AV25
(1M x 18)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
DNU
A
A
A
A
A
A
A
2
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
S
V
DD
DNU
DNU
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PRELIMINARY
Pin Configurations
(continued)
119-Ball Bump BGA
CY7C1370AV25 (512K x 36) - 7 x 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC
64M
V
DDQ
2
A
NC
A
DP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
DP
d
A
NC
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWS
c
V
SS
V
DD(1)
V
SS
BWS
d
V
SS
V
SS
V
SS
MODE
A
TDI
4
A
ADV/LD
V
DD
NC
CE
1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BWS
b
V
SS
V
DD(1)
V
SS
BWS
a
V
SS
V
SS
V
SS
NC
A
TDO
6
A
NC
A
DP
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
DP
a
A
32M
DNU
7
V
DDQ
NC
NC
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC
NC
V
DDQ
CY7C1370AV25
CY7C1372AV25
CY7C1372AV25 (1M x 18) - 7 x 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC
64M
V
DDQ
2
A
NC
A
NC
DQ
b
NC
DQ
b
NC
V
DD
DQ
b
NC
DQ
b
NC
DP
b
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWS
b
V
SS
V
DD(1)
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
4
A
ADV/LD
V
DD
NC
CE
1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
32M
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD(1)
V
SS
BWS
a
V
SS
V
SS
V
SS
SN
A
TDO
6
A
NC
A
DP
a
NC
DQ
a
NC
DQ
a
V
DD
NC
DQ
a
NC
DQ
a
NC
A
A
DNU
7
V
DDQ
NC
NC
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
NC
V
DDQ
NC
DQ
a
NC
NC
V
DDQ
3
PRELIMINARY
Pin Definitions (100-Pin TQFP)
x18 Pin Location
37, 36, 32–35,
44–50, 80–84, 99,
100
93, 94
x36 Pin Location
37, 36, 32–35,
44–50, 81-84, 99,
100
93, 94, 95, 96
Name
A0
A1
A
BWS
a
BWS
b
BWS
c
BWS
d
WE
I/O Type
Input-
Synchronous
Input-
Synchronous
Description
CY7C1370AV25
CY7C1372AV25
Address Inputs used to select one of the 266,144 ad-
dress locations. Sampled at the rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE
to conduct writes to the SRAM. Sampled on the rising
edge of CLK. BWS
a
controls DQ
a
and DP
a
, BWS
b
con-
trols DQ
b
and DP
b
, BWS
c
controls DQ
c
and DP
c
, BWS
d
controls DQ
d
and DP
d
.
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip ad-
dress counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is ad-
vanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only rec-
ognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
2
and CE
3
to
select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
3
to
select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
1
and CE
2
to
select/deselect the device.
88
88
Input-
Synchronous
Input-
Synchronous
85
85
ADV/LD
89
89
CLK
Input-Clock
98
98
CE
1
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
97
97
CE
2
92
92
CE
3
86
86
OE
Input-
Output Enable, active LOW. Combined with the synchro-
Asynchronous nous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the
first clock when emerging from a deselected state and
when the device has been deselected.
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW
the clock signal is recognized by the SRAM. When deas-
serted HIGH the clock signal is masked. Since deassert-
ing CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[17:0]
during the previous
clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE
is asserted LOW, the pins can behave as outputs. When
HIGH, DQ
a
–DQ
d
are placed in a three-state condition.
The outputs are automatically three-stated during the
data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
87
87
CEN
(a)58, 59, 62, 63,
68, 69, 72–73
(b)8, 9, 12, 13, 18,
19, 22–23
(a)52, 53, 56–59,
62, 63,
(b)68, 69, 72–75,
78, 79
(c)2, 3, 6–9, 12, 13,
(d)18, 19, 22–25,
28, 29
DQ
a
DQ
b
DQ
c
DQ
d
I/O-
Synchronous
4
PRELIMINARY
Pin Definitions (100-Pin TQFP)
(continued)
x18 Pin Location
74, 24
x36 Pin Location
51, 80, 1, 30
Name
DP
a
DP
b
DP
c
DP
d
MODE
I/O Type
I/O-
Synchronous
Description
CY7C1370AV25
CY7C1372AV25
Bidirectional Data Parity I/O lines. Functionally, these sig-
nals are identical to DQ
[31:0]
. During write sequences,
DP
a
is controlled by BWS
a
, DP
b
is controlled by BWS
b
,
DP
c
is controlled by BWS
c
, and DP
d
is controlled by
BWS
d
.
Mode Input. Selects the burst order of the device. Tied
HIGH selects the interleaved burst order. Pulled LOW
selects the linear burst order. MODE should not change
states during operation. When left floating MODE will de-
fault HIGH, to an interleaved burst order.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device. Should be connected to ground of
the system.
No connects. Reserved for address expansion to 512K
depths.
Do Not Use pins. These pins should be left floating.
31
31
Input
Strap Pin
15, 16, 41, 65, 66,
91
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
14
38, 39, 42, 43
15, 16, 41, 65, 66,
91
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
14
38, 39, 42, 43
V
DD
V
DDQ
V
SS
Power Supply
I/O Power
Supply
Ground
NC
DNU
-
-
Pin Definitions (119 BGA)
x18 Pin Location
P4, N4, A2, A3, A4,
A5, A6, B3, B5, C2,
C3, C5, C6, G4, R2,
R6, T2, T3, T5, T6
L5, G3
x36 Pin Location
P4, N4, A2, A3, A4,
A5, A6, B3, B5, C2,
C3, C5, C6, R2, R6,
G4, T3, T4, T5
L5, G5, G3, L3
Name
A0
A1
A
BWS
a
BWS
b
BWS
c
BWS
d
WE
I/O Type
Input-
Synchronous
Description
Address Inputs used to select one of the 266,144
address locations. Sampled at the rising edge of the
CLK.
Byte Write Select Inputs, active LOW. Qualified with
WE to conduct writes to the SRAM. Sampled on the
rising edge of CLK. BWS
a
controls DQ
a
and DP
a
,
BWS
b
controls DQ
b
and DP
b
, BWS
c
controls DQ
c
and DP
c
, BWS
d
controls DQ
d
and DP
d
.
Write Enable Input, active LOW. Sampled on the ris-
ing edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip ad-
dress counter or load a new address. When HIGH
(and CEN is asserted LOW) the internal burst
counter is advanced. When LOW, a new address can
be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW in order
to load a new address.
Clock Input. Used to capture all synchronous inputs
to the device. CLK is qualified with CEN. CLK is only
recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
2
and
CE
3
to select/deselect the device.
Input-
Synchronous
H4
H4
Input-
Synchronous
Input-
Synchronous
B4
B4
ADV/LD
K4
K4
CLK
Input-Clock
E4
E4
CE
1
Input-
Synchronous
5
FPGA/CPLD
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