D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
CY23S08
3.3 V Zero Delay Buffer
3.3 V Zero Delay Buffer
Features
■
■
■
Zero input output propagation delay, adjustable by capacitive
load on FBK input
Multiple configurations (see
Table 3
on page 4)
Multiple low-skew outputs
❐
45-ps typical output-output skew (–1)
❐
Two banks of four outputs that can be tristated by two select
inputs
10 MHz to 140 MHz operating range
65-ps typical cycle-to-cycle jitter (–1, –1H)
Advanced 0.65-μm complementary metal oxide semiconductor
(CMOS) technology
Space-saving 16-pin small outline integrated circuit (SOIC)
package
3.3-V operation
Spread Aware
The CY23S08 has two banks of four outputs each, which can be
controlled by the Select inputs as shown in
Table 2
on page 4. If
all output clocks are not required, Bank B can be tristated. The
select inputs also enable the input clock to be directly applied to
the output for chip and system testing purposes.
The CY23S08 PLL enters a power-down state when there are no
rising edges on the REF input. In this mode, all outputs are
tristated and the PLL is turned off, resulting in less than 50
μA
of
current draw. The PLL shuts down in two additional cases as
shown in
Table 2
on page 4.
Multiple CY23S08 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY23S08 is available in five different configurations, as
shown in
Table 3
on page 4. The CY23S08–1 is the base part,
where the output frequencies equal the reference if there is no
counter in the feedback path. The CY23S08–1H is the high-drive
version of the –1, and rise and fall times on this device are much
faster.
The CY23S08–2 enables you to obtain 2X and 1X frequencies
on each output bank. The exact configuration and output
frequencies depends on which output drives the feedback pin.
The CY23S08–2H is the high drive version of the –2, and rise
and fall times on this device are much faster.
The CY23S08–4 enables you to obtain 2X clocks on all outputs.
Therefore, the part is versatile, and can be used in a variety of
applications.
■
■
■
■
■
■
Functional Description
The CY23S08 is a 3.3-V zero delay buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom, and
other high-performance applications.
The part has an on-chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback must be driven into
the FBK pin, and obtained from one of the outputs. The
input-to-output propagation delay is less than 350 ps and
output-to-output skew is less than 250 ps.
Logic Block Diagram
/2
REF
PLL
MUX
FBK
CLKA1
CLKA2
CLKA3
Extra Divider (–4)
S2
S1
CLKA4
Select Input
Decoding
/2
CLKB1
CLKB2
CLKB3
Extra Divider (–2, –2H)
CLKB4
Cypress Semiconductor Corporation
Document Number : 38-07265 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 12, 2010
[+] Feedback
CY23S08
Contents
Pinouts ..............................................................................
Spread Aware....................................................................
Maximum Ratings.............................................................
Operating Conditions.......................................................
Electrical Characteristics for CY23S08SXC-xx
Commercial Temperature Devices..................................
Switching Characteristics for CY23S08SXC-xx
Commercial Temperature Devices..................................
Switching Waveforms ......................................................
Test Circuits......................................................................
Ordering Information........................................................
Ordering Code Definition.............................................
3
4
5
5
5
5
7
8
9
9
Package Drawings and Dimensions .............................
Acronyms ........................................................................
Document Conventions .................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
10
12
12
13
14
14
14
14
Document Number : 38-07265 Rev. *M
Page 2 of 13
[+] Feedback
CY23S08
Pinouts
Figure 1. Pin Configuration – 16-Pin Package (Top View)
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
Table 1. Pin Definition
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
[1]
CLKA1
[2]
CLKA2
[2]
V
DD
GND
CLKB1
[2]
CLKB2
[2]
S2
[3]
S1
[3]
CLKB3
[2]
CLKB4
[2]
GND
V
DD
CLKA3
[2]
CLKA4
[2]
FBK
Signal
Clock output, Bank A
Clock output, Bank A
3.3-V supply
Ground
Clock output, Bank B
Clock output, Bank B
Select input, bit 2
Select input, bit 1
Clock output, Bank B
Clock output, Bank B
Ground
3.3-V supply
Clock output, Bank A
Clock output, Bank A
PLL feedback input
Description
Input reference frequency, 5-V tolerant input
Notes
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
Document Number : 38-07265 Rev. *M
Page 3 of 13
[+] Feedback
CY23S08
Table 2. Select Input Decoding
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Tristate
Driven
Driven
Driven
CLOCK B1–B4
Tristate
Tristate
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
Y
N
Y
N
Table 3. Available CY23S08 Configurations
Device
CY23S08–1
CY23S08–1H
CY23S08–2
CY23S08–2H
CY23S08–2
CY23S08–2H
CY23S08–4
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank A
Bank B
Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
Reference
2 X Reference
2 X Reference
2 X Reference
Reference
Reference
Reference/2
Reference/2
Reference
Reference
2 X Reference
Bank B Frequency
Spread Aware
Many systems designed now use the Spread Spectrum frequency timing generation (SSFTG) technology. Cypress is one of the
pioneers of SSFTG development, and designed this product so as not to filter off the Spread Spectrum feature of the Reference input,
assuming it exists. When a zero delay buffer does not pass through the SS feature, the result is a significant amount of tracking skew
which may cause problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology, see Cypress’s application note
EMI Suppression Techniques with Spread
Spectrum Frequency Timing Generator (SSFTG) ICs.
Note
4. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2.
Document Number : 38-07265 Rev. *M
Page 4 of 13
[+] Feedback
GD32 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
