Hardware Design Guide
September 8, 2004
MARS2G5 P-VC-XTRM (TMPRFE2G5)
Datamapper
™
2488/622/155 Mbits/s SONET/SDH x 10/100/1000 Mbits/s Ethernet
1 Introduction
The documentation package for the
Datamapper
device consists of the following documents, available on a password pro-
tected website:
Datamapper
Product Description
Datamapper
System Design Guide
Datamapper
Hardware Design Guide (this document)
Datamapper
Register Description
Datamapper
Resource Guide
This document describes the Agere Systems
Datamapper
device hardware interfaces. Information relevant to the use of the
device in a board design is covered, including the following:
Ball descriptions and assignments
Electrical characteristics
Timing specifications
Packaging diagrams
Thermal characteristics
This document is applicable for the
Datamapper
device versions listed in
Table 12-1 Ordering Information, on page 92.
To contact Agere, please see the last page of this document. To access the above documents, please click on the following
address:
http://www.agere.com/mappers/Datamapper/
or contact your Agere representative.
Agere - Proprietary
Hardware Design Guide
September 8, 2004
MARS2G5 P-VC-XTRM (TMPRFE2G5) Datamapper
2488/622/155 Mbits/s SONET/SDH x 10/100/1000 Mbits/s Ethernet
Table of Contents
Contents
Page
2 Introduction .........................................................................................................................................................................1
3 Ball Information ...................................................................................................................................................................8
3.1 Package Diagram ........................................................................................................................................................8
3.2 Ball Assignment by Signal Name Order ......................................................................................................................9
3.3 Pin Types ...................................................................................................................................................................20
3.4 Ball Description ..........................................................................................................................................................21
4 Pin Matrix ..........................................................................................................................................................................54
5 Electrical Characteristics ..................................................................................................................................................57
5.1 Absolute Maximum Ratings .......................................................................................................................................57
5.2 Handling Precautions ................................................................................................................................................57
5.3 Thermal Parameters (Definitions and Values) ...........................................................................................................57
5.4 Reliability ...................................................................................................................................................................58
5.5 Recommended Operating Conditions .......................................................................................................................59
5.6 Recommended Power Supply Decoupling ................................................................................................................59
5.6.1 Digital Supply Decoupling ................................................................................................................................59
5.6.2 Analog Supply Decoupling ...............................................................................................................................59
5.7 Recommended Powerup Sequence ..........................................................................................................................61
5.8 Power Consumption ..................................................................................................................................................61
5.9 Interface Characteristics ............................................................................................................................................62
5.9.1 LVTTL Interface Characteristics .......................................................................................................................62
5.9.2 LVDS Interface Characteristics ........................................................................................................................63
5.9.3 SSTL_2 Class I Interface Characteristics ........................................................................................................64
5.9.4 LVPECL Interface Characteristics ....................................................................................................................65
5.9.5 CML Interface Characteristics ..........................................................................................................................65
6 Timing Characteristics ......................................................................................................................................................66
6.1 SPI-3 Interface Timing ...............................................................................................................................................66
6.2 FCRAM Interface Timing ...........................................................................................................................................67
6.3 SB SRAM Interface Timing ........................................................................................................................................69
6.4 SS-SMII Interface Timing ..........................................................................................................................................70
6.4.1 SS-SMII Output Clock Skew ............................................................................................................................71
6.5 TBI Interface Timing ..................................................................................................................................................71
6.6 GMII Interface Timing ................................................................................................................................................71
6.7 MDIO Interface Timing ..............................................................................................................................................72
6.8 SOAC Interface Timing ..............................................................................................................................................72
6.9 JTAG Interface Timing ...............................................................................................................................................74
6.10 Microprocessor Interface Timing .............................................................................................................................74
6.11 System Interface Timing ..........................................................................................................................................75
7 Microprocessor Interface Timing ......................................................................................................................................75
7.1 Introduction ................................................................................................................................................................75
7.2 (Host_BMode[1:0] = 00) (MC68360) .........................................................................................................................76
7.2.1 Asynchronous Write Cycle (Host_BMode[1:0] = 00) ........................................................................................76
7.2.2 Asynchronous Read Cycle ...............................................................................................................................77
7.3 Host_BMode[1:0] = 01 (MPC860) .............................................................................................................................79
7.3.1 Synchronous Write Cycle (Host_BMode[1:0] = 01) ..........................................................................................79
7.3.2 Synchronous Read Cycle (Host_BMode[1:0] = 01) .........................................................................................80
7.4 (Host_BMode[1:0] = 10) (i960) ..................................................................................................................................82
7.4.1 Multiplexed Synchronous Write Cycle Host_BMode[1:0] = 10 .........................................................................82
7.4.2 Synchronous Read Cycle (Host_BMode[1:0] = 10) .........................................................................................84
8 Hardware Design File References ....................................................................................................................................86
9 JTAG Boundary-Scan .......................................................................................................................................................86
9.1 The Principle of Boundary-Scan Architecture ............................................................................................................86
9.2 Instruction Register ....................................................................................................................................................87
Agere Systems Inc.
Agere - Proprietary
3
MARS2G5 P-VC-XTRM (TMPRFE2G5) Datamapper
2488/622/155 Mbits/s SONET/SDH x 10/100/1000 Mbits/s Ethernet
Hardware Design Guide
September 8, 2004
Table of Contents
(continued)
Contents
Page
9.3 Identification Code Register ......................................................................................................................................87
9.4 Boundary-Scan Register ...........................................................................................................................................87
9.5 System Configuration Recommendations .................................................................................................................88
10 GigE, TBI, and GMII Interface Usage Guidelines ...........................................................................................................88
11 1605 Ball FBGA Diagrams .............................................................................................................................................88
11.1 1605 FCBGA Physical Dimension ...........................................................................................................................88
12 Jitter Requirement and Specification ..............................................................................................................................92
13 Ordering Information .......................................................................................................................................................92
14 Change History ...............................................................................................................................................................92
14.1 September 8, 2004 ..................................................................................................................................................94
4
Agere - Proprietary
Agere Systems Inc.
Hardware Design Guide
September 8, 2004
MARS2G5 P-VC-XTRM (TMPRFE2G5) Datamapper
2488/622/155 Mbits/s SONET/SDH x 10/100/1000 Mbits/s Ethernet
Table of Contents
(continued)
Figures
Page
Figure 1-1. Datamapper Functional Block Diagram ...............................................................................................................2
Figure 2-1. Package Ball Diagram..........................................................................................................................................8
Figure 4-1. 1.0 V PLL Supply Voltage ..................................................................................................................................59
Figure 4-2. 1.2 V CDR Supply Voltage.................................................................................................................................60
Figure 4-3. 1.2 V Analog Supply Voltage .............................................................................................................................60
Figure 4-4. SSTL Interface Buffers Voltage Reference ........................................................................................................60
Figure 4-5. CML 1.2 V Receiver Termination Voltage..........................................................................................................61
Figure 4-6. LVDS Reference Voltage Inputs ........................................................................................................................61
Figure 4-7. Single-Ended Signal Rise/Fall Time Specification .............................................................................................63
Figure 4-8. Single-Ended Clock and Data Timing Specification...........................................................................................63
Figure 4-9. LVDS Signal Rise/Fall Time Specification .........................................................................................................64
Figure 5-1. Relationship Between SBSRAM0OE_N, SBSRAM1OE_N and SBSRAM0CLKOUT, SBSRAM1CLKOUT......70
Figure 5-2. Transmit TOAC Timing ......................................................................................................................................73
Figure 5-3. Receive TOAC Timing .......................................................................................................................................73
Figure 6-1. Microprocessor Interface Asynchronous Write Cycle (Host_BMode[1:0] = 00) .................................................76
Figure 6-2. Microprocessor Interface Asynchronous Read Cycle (Host_BMode[1:0] = 00) .................................................78
Figure 6-3. Microprocessor Interface Synchronous Write Cycle (Host_BMode[1:0] = 01) ...................................................79
Figure 6-4. Microprocessor Interface Synchronous Read Cycle (Host_BMode[1:0] = 01)...................................................81
Figure 6-5. Microprocessor Interface Multiplexed Synchronous Write Cycle (Host_BMode[1:0] = 10)................................83
Figure 6-6. Microprocessor Interface Read Cycle (Host_BMode[1:0] = 10).........................................................................85
Figure 8-1. IEEE® 1149.1 Boundary-Scan Architecture ......................................................................................................86
Figure 10-1. 1605 FCBGA Physical Dimension ...................................................................................................................89
Figure 10-2. 1605 FCBGA Physical Dimension ...................................................................................................................91
Agere Systems Inc.
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Agere - Proprietary
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