IDT54/74FCT16373T/AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS 16-BIT
TRANSPARENT LATCH
IDT54/74FCT16373T/AT/CT
FEATURES:
−
−
−
−
−
−
−
−
−
−
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK
(o) (Output Skew) < 250ps
Low input and output leakage
≤1µ
A (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 5V ±10%
High drive outputs (-32mA I
OH
, 64mA I
OL
)
Power off disable outputs permit “live insertion”
Typical V
OLP
(Output Ground Bounce) < 1.0V at V
CC
= 5V, T
A
=
25°C
Available in the following packages:
•
Industrial: SSOP, TSSOP, TVSOP
•
Military: CERPACK
DESCRIPTION:
The FCT16373T 16-bit transparent D-type latch is built using advanced
dual metal CMOS technology. These high-speed, low-power latches are
ideal for temporary storage of data. They can be used for implementing
memory address latches, I/O ports, and bus drivers. The Output Enable and
Latch Enable controls are organized to operate each device as two 8-bit
latches, or one 16-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
The FCT16373T is ideally suited for driving high-capacitance loads and
low-impedance backplanes. The output buffers are designed with power off
disable capability to allow "live insertion" of boards when used as backplane
drivers.
FUNCTIONAL BLOCK DIAGRAM
1
OE
2
OE
1
LE
1
D
1
2
LE
D
1
O
1
2
D
1
D
2
O
1
C
C
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
c
1999 Integrated Device Technology, Inc.
NOVEMBER 2000
DSC-5454/-
IDT54/74FCT16373T/AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
1
OE
1
O
1
1
O
2
ABSOLUTE MAXIMUM RATINGS
(1)
48
47
46
45
44
43
42
41
40
39
38
1
LE
1
D
1
1
D
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SO48-1
SO48-2
SO48-3
E48-1
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
5v16-link
GND
1
O
3
1
O
4
GND
1
D
3
1
D
4
V
CC
1
O
5
1
O
6
V
CC
1
D
5
1
D
6
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
GND
1
O
7
1
O
8
2
O
1
2
O
2
GND
1
D
7
1
D
8
2
D
1
2
D
2
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
5v16-link
37
36
35
34
33
32
31
30
29
28
27
26
25
NOTE:
1. This parameter is measured at characterization but not tested.
GND
2
O
3
2
O
4
GND
2
D
3
2
D
4
PIN DESCRIPTION
Pin Names
xDx
xLE
xOE
xOx
Description
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-State Outputs
V
CC
2
O
5
2
O
6
V
CC
2
D
5
2
D
6
FUNCTION TABLE
(1)
xDx
H
L
X
NOTE:
1. H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High-impedance
GND
2
O
7
2
O
8
2
OE
GND
2
D
7
2
D
8
2
LE
Inputs
xLE
H
H
X
xOE
L
L
H
Outputs
xOx
H
L
Z
SSOP/ TSSOP/ TVSOP/ CERPACK
TOP VIEW
2
IDT54/74FCT16373T/AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ±10%; Military: T
A
= -55°C to +125°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
V
I
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
Min.
2
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
0.8
±1
±1
±1
±1
±1
±1
–1.2
–250
—
500
V
mA
mV
µA
µA
Unit
V
V
µA
5v16-link
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
O
V
OH
Parameter
Output Drive Current
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Max., V
O
= 2.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –3mA
I
OH
= –12mA MIL
I
OH
= –15mA IND
I
OH
= –24mA MIL
I
OH
= –32mA IND
(4)
V
OL
I
OFF
Output LOW Voltage
Input/Output Power Off Leakage
(5)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
O
≤
4.5V
I
OL
= 48mA MIL
I
OL
= 64mA IND
—
—
±1
µA
—
0.2
0.55
V
2
3
—
V
Min.
–50
2.5
2.4
Typ.
(2)
—
3.5
3.5
Max.
–180
—
—
Unit
mA
V
V
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at T
A
= -55°C.
3
IDT54/74FCT16373T/AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
xOE = GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi =10MHz
50% Duty Cycle
xOE = GND
xLE
=
V
CC
One Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
xOE = GND
xLE = V
CC
Sixteen Bits Toggling
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
60
Max.
1.5
100
Unit
mA
µ A/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
0.6
1.5
mA
—
0.9
2.3
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
2.4
4.5
(5)
—
6.4
16.5
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
4
IDT54/74FCT16373T/AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16373T
Ind.
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK
(o)
Parameter
Propagation Delay
xDx to xOx
Propagation Delay
xLE to xOx
Output Enable Time
Output Disable Time
Set-up Time HIGH or LOW, xDx to xLE
Hold Time HIGH or LOW, xDx to xLE
xLE Pulse Width HIGH
Output Skew
(3)
Mil.
FCT16373AT
Ind.
Mil.
FCT16373CT
Ind.
Mil.
Condition
(1)
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Unit
C
L
= 50pF
1.5
8
1.5 8.5
1.5
5.2
1.5
5.6
1.5
3.6
1.5
5.1 ns
R
L
= 500Ω
2
1.5
1.5
2
1.5
6
—
13
12
7.5
—
—
—
0.5
2
1.5
1.5
2
1.5
6
—
15
13.5
10
—
—
—
0.5
2
1.5
1.5
2
1.5
5
—
8.5
6.5
5.5
—
—
—
0.5
2
1.5
1.5
2
1.5
6
—
9.8
7.5
6.5
—
—
—
0.5
2
1.5
1.5
2
1.5
5
—
3.7
4.4
3.9
—
—
—
0.5
2
1.5
1.5
2
1.5
6
—
8
6.3
5.9
—
—
—
0.5
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5
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