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CY26114
One-PLL Clock Generator
Features
■
■
■
Benefits
■
■
■
Integrated phase-locked loop
Low skew, low jitter, high accuracy outputs
3.3V operation with 2.5 V output option
Part Number
CY26114
Outputs
4
Input Frequency
25 MHz Crystal Input
Internal PLL with up to 333 MHz internal operation.
Meets critical timing requirements in complex system designs.
Enables application compatibility.
Output Frequency Range
2 copies of 100 MHz, 1 copy of 50 MHz,
1 copy 25, 33, 50, and 66 MHz (frequency selectable)
Logic Block Diagram
XIN
XOUT
OSC.
Q
Φ
VCO
P
OUTPUT
MULTIPLEXER
AND
DIVIDERS
100MHz
100MHz
50MHz
(frequency selectable)
PLL
FS0
FS1
25/33/50/66MHz
VDDL
VDD
AVDD
AVSS
VSS
VSSL
CLK4 Frequency Select Options
FS1
0
0
1
1
FS0
0
1
0
1
CLK 4
25
33
50
66
Units
MHz
MHz
MHz
MHz
Cypress Semiconductor Corporation
Document #: 38-07098 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 15, 2008
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CY26114
Pin Configurations
Figure 1. CY26114, 16-Pin TSSOP
XIN
VDD
AVDD
FS0
AVSS
VSSL
LCLK1
LCLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
CLK4
CLK3
VSS
N/C
VDDL
FS1
N/C
Table 1. Pin Definitions
Name
XIN
V
DD
AV
DD
FS0
AV
SS
V
SSL
LCLK1
LCLK2
N/C
FS1
V
DDL
N/C
VSS
CLK3
CLK4
XOUT
[1]
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
Reference Crystal Input
Voltage Supply
Analog Voltage Supply
Frequency Select 0
Analog Ground
LCLK Ground
100 MHz Output clock at V
DDL
Level
100 MHz Output clock at V
DDL
Level
No Connect
Frequency Select 1
LCLK Voltage Supply (2.5V or 3.3V)
No Connect
Ground
50 MHz Output Clock
25, 33, 50, and 66 MHz Clock Output (frequency selectable)
Reference Crystal Output
Note
1. Float XOUT if XIN is externally driven.
Document #: 38-07098 Rev. *B
Page 2 of 5
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CY26114
Absolute Maximum Conditions
Parameter
V
DD
V
DDL
T
J
Description
Supply Voltage
IO Supply Voltage
Junction Temperature
Digital Inputs
Digital Outputs Referred to V
DD
Digital Outputs Referred to V
DDL
Electro-Static Discharge
Min
–0.5
Max
7.0
7.0
125
AV
DD
+ 0.3
V
DD
+ 0.3
V
DDL
+0.3
Unit
V
V
°C
V
V
V
kV
AV
SS
– 0.3
V
SS
– 0.3
V
SS
– 0.3
2
Recommended Operating Conditions
Parameter
V
DD
V
DDL
T
A
C
LOAD
f
REF
t
PU
Description
Operating Voltage
Operating Voltage
Ambient Temperature
Maximum Load Capacitance
Reference Frequency
Power Up Time—for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
Min
3.0
2.375
0
Typ
3.3
2.5
Max
3.6
2.625
70
15
500
Unit
V
V
°C
pF
MHz
ms
25
0.05
DC Electrical Characteristics
Parameter
[2]
I
OH
I
OL
I
OH
I
OL
V
IH
V
IL
I
VDD
I
VDDL
I
VDDL
Name
Output High Current
Output Low Current
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Supply Current
Supply Current
Supply Current
Description
V
OH
= V
DD
– 0.5, V
DD
/V
DDL
= 3.3V
V
OL
= 0.5, V
DD
/V
DDL
= 3.3V
V
OH
= V
DDL
– 0.5, V
DDL
=2.5V
V
OL
= 0.5, V
DDL
= 2.5V
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
AV
DD
/V
DD
Current
V
DDL
Current (V
DDL
= 3.6V)
V
DDL
Current (V
DDL
= 2.625V)
Min
12
12
8
8
0.7
Typ
24
24
16
16
Max
Unit
mA
mA
mA
mA
VDD
VDD
mA
mA
mA
0.3
25
20
15
AC Electrical Characteristics
Parameter
[2]
Name
DC
Output Duty Cycle
t
3
t
3
t
4
t
4
t5
t9
t10
Rising Edge Rate
Rising Edge Rate
Falling Edge Rate
Falling Edge Rate
Skew
Clock Jitter
PLL Lock Time
Description
Duty cycle is defined in
Figure 2;
t1/t2, 50% of
V
DD
Output clock rise time, 20%–80% of
V
DD
/V
DDL
= 3.3V
Output clock rise time, 20%–80% of
V
DDL
= 2.5V
Output clock fall time, 80%–20% of
V
DD
/V
DDL
= 3.3V
Output clock fall time, 80%–20% of
V
DDL
= 2.5V
Delay between related outputs at rising edge
Peak to peak period jitter
Min
45
0.8
0.6
0.8
0.6
Typ
50
1.4
1.2
1.4
1.2
250
200
3
Max
55
Unit
%
V/ns
V/ns
V/ns
V/ns
ps
ps
ms
Note
2. Not 100% tested.
Document #: 38-07098 Rev. *B
Page 3 of 5
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CY26114
Figure 2. Duty Cycle Definitions: DC = t2/t1
t1
t2
CLK
50%
50%
Figure 3. Rise Time and Fall Time Definitions
t3
80%
t4
CLK
20%
Figure 4. Test Circuit
V
DD
0.1
μF
OUTPUTS
CLK out
C
LOAD
AV
DD
0.1
μF
GND
Ordering Information
Ordering Code
CY26114ZC
[3]
CY26114KZC
CY26114KZCT
Package Name
Z16
Z16
Z16
Package Type
16-Pin TSSOP
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
Operating Range
Commercial
Commercial
Commercial
Operating Voltage
3.3V
3.3V
3.3V
Note
3. Not recommended for new designs.
Document #: 38-07098 Rev. *B
Page 4 of 5
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