AUSTIN SEMICONDUCTOR, INC.
AS42C4064 883C
64K x 4 VRAM
Limited Supply - Consult Factory
VRAM
AVAILABLE AS MILITARY
SPECIFICATION
• MIL-STD-883
64K x 4 DRAM
WITH 256 x 4 SAM
PIN ASSIGNMENT (Top View)
24-Pin DIP
(D-11)
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Industry standard pinout, timing and functions
High-performance, CMOS silicon-gate process
Single +5V
±10%
power supply
Inputs and outputs are fully TTL and CMOS
compatible
Refresh modes:
/
R
/
A
/
S-ONLY,
/
C
/
A
/
S-BEFORE-/R
/
A
/
S, and
HIDDEN
256-cycle refresh within 4ms
Optional PAGE MODE access cycles
Dual port organization: 64K x 4 DRAM port
256 x 4 SAM port
BIT MASK WRITE mode capability on DRAM port
No refresh required for serial access memory
Fast access times: 100ns parallel, 30ns serial
Specifications guaranteed over full military tempera-
ture range (-55°C to +125°C)
SC
SDQ1
SDQ2
1
2
3
24
23
Vss
SDQ4
SDQ3
SE
DQ4
DQ3
CAS
A0
A1
A2
A3
A7
OPTIONS
• Timing (DRAM, SAM)
100ns, 30ns
120ns, 35ns
• Packages
Ceramic DIP (400 mil)
NOTE: Consult factory for other package options.
22
ED
TR/OE
4
D
21
20
DQ1
5
E N NS
M
DQ2
I G
19
M
ME/WE
6
Y
18
7
O
E S
LI
–
T
C
D
RAS
I
8
17
E
AB
MARKING
R E W
VAIL
A6
9
16
T
N
ED A
15
A5
10
O R
IT
N O
IM
14
A4
11
13
Vcc
12
F
–L
-10
-12
C
No. 107
GENERAL DESCRIPTION
The AS42C4064 883C is a high-speed, dual port CMOS
dynamic random access memory, or video RAM (VRAM)
containing 262,144 bits. These bits may be accessed by a 4-
bit-wide DRAM port or by a 256 x 4 bit serial access memory
(SAM) port. Data may be transferred bidirectionally be-
tween the DRAM and the SAM.
The DRAM portion of the VRAM is functionally identical
to the MT4067 (64K x 4) bit DRAM. Four 256-bit data
registers make up the serial access memory portion of the
VRAM. Data I/O and internal data transfer are accom-
plished using three separate bidirectional data paths; the
4-bit random access I/O port, the four internal 256-bit wide
paths between the DRAM and the SAM, and the 4-bit serial
I/O port for the SAM. The rest of the circuitry consists of the
control, timing and address decoding logic.
Each of the ports may be operated asynchronously and
independently of the other except when data is being trans-
ferred internally between them. As with all DRAMs, the
VRAM must be refreshed in order to maintain data. The
refresh cycles must be timed so that all 256 combinations of
/
R
/
A
/
S addresses are executed at least every 4ms (regardless
of sequence). Austin Semiconductor recommends evenly
spaced refresh cycles for maximum data integrity. An inter-
nal transfer between the DRAM and the SAM counts as a
refresh cycle. The SAM portion of the VRAM is fully static
and does not require any refresh.
AS42C4064 883C
REV. 3/97
DS000013
3-1
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
.
AUSTIN SEMICONDUCTOR, INC.
AS42C4064 883C
64K x 4 VRAM
Limited Supply - Consult Factory
EQUIVALENT FUNCTIONAL BLOCK DIAGRAM
COLUMN ADDRESS
LATCH/BUFFER
8
4
COLUMN DECODER
256
8
4
M
A
S
K
WRITE
CONTROL
LOGIC
DRAM
OUTPUT
BUFFERS
DQ1
SENSE AMPLIFIERS
256
4
DQ4
4
DRAM
INPUT
BUFFERS
4
ROW DECODER
ROW ADDRESS
LATCH/BUFFER
A0-A7
8
8
256
256 x 256 x 4
DRAM ARRAY
TIMING
GENERATOR
&
CONTROL
LOGIC
256
TRANSFER GATE
SAM
*
256
8
REFRESH
COUNTER
RAS
CAS
TR/OE
ME/WE
SC
SE
TRANSFER
CONTROL
SAM
OUTPUT
BUFFERS
SDQ1
SAM LOCATION
DECODER
SAM ADDRESS
LATCH/BUFFER
SAM ADDRESS
COUNTER
4
4
SAM
INPUT
BUFFERS
4
SDQ4
8
8
8
* The SAM register is 512 bits wide. Auto wrap around will not occur at the 257th serial clock pulse, thus requiring the serial
pointer to be reset back to zero, using a read or write transfer cycle.
AS42C4064 883C
REV. 3/97
DS000013
3-2
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
.
AUSTIN SEMICONDUCTOR, INC.
AS42C4064 883C
64K x 4 VRAM
Limited Supply - Consult Factory
PIN DESCRIPTIONS
SYMBOL
SC
SDQ1-SDQ4
/
T
/
R//O
/
E
FUNCTION
Input
Input/
Output
Input
DESCRIPTION
Serial Clock: Clock input to the serial address counter for the SAM
registers
Serial Data I/O: Input, output or High-Z
Transfer Enable: Enables an internal TRANSFER operation at
/
R
/
A
/
S (H
>
L), or
Output Enable: Enables the DRAM output buffers when taken LOW
after
/
R
/
A
/
S goes LOW (/C
/
A
/
S must also be LOW), otherwise the output
buffers are in High-Z
DQ1-DQ4
?
M
/
E/?W
/
E
Input/
Output
Input
DRAM Data I/O: Inputs, outputs or High-Z and/or
mask data inputs: For MASKED-WRITE cycle only
Mask Enable: If
?
M
/
E/?W
/
E is LOW at the falling edge of
/
R
/
A
/
S a MASKED-
WRITE cycle is performed, or
Write Enable: W
/
E is used to select a READ (?W
/
E = H) or WRITE (?W
/
E =
?
L) cycle when accessing the DRAM. This includes a DRAM-TO-SAM
TRANSFER (?W
/
E = H) or SAM-TO-DRAM TRANSFER (?W
/
E = L).
/
R
/
A
/
S
A0-A7
Input
Input
Row Address Strobe:
/
R
/
A
/
S is used to clock in the 8 row address bits
and as a strobe for the MASK ENABLE and TRANSFER functions.
Address Inputs: For the DRAM operation, these inputs are multiplexed
and clocked by
/
R
/
A
/
S and
/
C
/
A
/
S to select 4 bits out of the 256K
available. During TRANSFER operations, A0 to A7 indicate the DRAM
row being accessed (when
/
R
/
A
/
S goes LOW) and the SAM start
address (when
/
C
/
A
/
S goes LOW).
Power Supply: +5V
±10%
Column Address Strobe:
/
C
/
A
/
S is used to clock in the 8 column address
bits and enable the DRAM output buffers (/T
/
R/?O
/
E must also be LOW).
Serial Port Enable:
/
S
/
E enables the serial I/O buffers and allows a
serial READ or WRITE operation to occur; otherwise the output buffers
are in High-Z.
/
S
/
E is also used during a TRANSFER operation to
indicate whether a SAM-TO-DRAM TRANSFER or a SERIAL-INPUT-
MODE ENABLE cycle is performed.
Ground
V
CC
/
C
/
A
/
S
/
S
/
E
Supply
Input
Input
V
SS
Supply
AS42C4064 883C
REV. 3/97
DS000013
3-3
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
.
AUSTIN SEMICONDUCTOR, INC.
FUNCTIONAL DESCRIPTION
The VRAM can be divided into three functional blocks;
the DRAM, the transfer control circuitry, and the serial
access memory (SAM). All of the operations described
below are also shown in the AC Timing Diagrams of this
section and are summarized in the Truth Table.
Note:
For dual function pins, the function that is not being
discussed will be surrounded by parenthesis. For
example, the
/
T
/
R/
/
O
/
E pin will be shown as
/
T
/
R/(
/
O
/
E) in
references to transfer operations.
AS42C4064 883C
64K x 4 VRAM
Limited Supply - Consult Factory
DRAM OPERATION
The DRAM portion of the VRAM is functionally identical
to standard 64K x 4 DRAMs. However, because several of
the DRAM control pins are used for additional functions on
this part, several conditions that were undefined or “don’t
care” states for the DRAM are specified for the VRAM.
These conditions are highlighted in the following discus-
sion.
READ/WRITE Cycles
The 16 address bits that are used to select a 4-bit word
from the 65,536 x 4 available are latched into the chip using
the A0-A7,
/
R
?
A
/
S, and
/
CA
/
S inputs. First, the 8 row-address
?
bits are set up on the address inputs and clocked into the
part when
/
RA
/
S transitions from HIGH-to-LOW. Next, the
?
8 column address bits are set up on the address inputs and
clocked-in when
/
CA
/
S goes from HIGH-to-LOW.
/
For single port DRAMs, the
?
O
/
E pin is a “don’t care” when
/
R
/
A
/
S goes LOW. For the VRAM, (/T
/
R)/?O
/
E is used, when
/
R
/
A
/
S goes LOW, to select between an internal transfer
operation and a DRAM operation. (/T
/
R)/?O
/
E must be HIGH
at the
/
R
?
A
/
S HIGH-to-LOW transition for a DRAM port
READ or WRITE operation.
If (?M
/
E)/?W
/
E is HIGH when
/
C
/
A
/
S goes LOW, a DRAM
READ operation is performed and the data from the memory
cells selected will appear at the DQ1-DQ4 port. The (/T
/
R)/
?
O
/
E input must be LOW to enable the DRAM output port.
For single port DRAMS,
?
W
/
E is a “don’t care” when
/
R
?
A
/
S
goes LOW. For the VRAM, (?M
/
E)/?W
/
E is used, when
/
R
?
A
/
S
goes LOW, to select between a MASKED-WRITE cycle and
a normal WRITE cycle. If (?ME)/?W
/
E is LOW at the
/
R
/
A
/
S
/
HIGH-to-LOW transition, a MASKED-WRITE operation is
selected. For a normal DRAM WRITE operation, (?ME)/
/
?
W
/
E must be HIGH at the
/
RA
/
S HIGH-to-LOW transition.
/
(?M
/
E)/?WE is a “don’t care” at the R
/
AS HIGH-to-LOW
/
/ /
transition for a DRAM READ cycle.
If (?M
/
E)/?W
/
E is LOW when
/
C
/
A
/
S goes LOW, a DRAM
WRITE operation is performed and the data present on the
DQ1-DQ4 port will be written into the selected memory
cells. If
?
M
/
E/(?W
/
E) is LOW when
/
R
/
A
/
S goes LOW, the input
data will be “masked” before being stored in the DRAM.
The VRAM can perform all the normal DRAM cycles
including EARLY-WRITE, LATE-WRITE, READ-WRITE,
READ-MODIFY-WRITE, PAGE-MODE READ, PAGE-
MODE WRITE and PAGE-MODE READ-MODIFY-
WRITE. Refer to the AC timing parameters and diagrams
in this data sheet for more details on these operations.
MASKED-WRITE
If
?
M
/
E/(?W
/
E) is LOW at the
/
R
/
AS HIGH-to-LOW transi-
/
tion, the data (mask data) present on the DQ1-DQ4 inputs
will be written into the bit mask data register. The mask
data acts as an individual write enable for each of the four
DQ-DQ4 pins. If a LOW (logic 0) is written to a mask data
register bit, the input port for that bit is disabled during the
subsequent WRITE operation and no new data will be
written to that DRAM cell location. A HIGH (logic 1) on a
mask data register bit enables the input port and allows
normal WRITE operations to proceed. Note that
/
C
/
A
/
S is still
HIGH. When C
/
AS goes LOW, the bits present on the DQ1-
/ /
DQ4 inputs will be written to the DRAM (if the mask data
bit was HIGH) or ignored (if the mask data bit was LOW).
The DRAM contents that correspond to the masked bits will
not be changed during the WRITE cycle. Since the mask
data register is reset (to all 1s) at the end of every MASKED-
WRITE cycle, new mask data must be supplied at the
beginning of each MASKED-WRITE cycle. An example of a
typical MASKED-WRITE cycle is shown in Figure 1.
AS42C4064 883C
REV. 3/97
DS000013
3-4
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
.
AUSTIN SEMICONDUCTOR, INC.
AS42C4064 883C
64K x 4 VRAM
Limited Supply - Consult Factory
RAS
CAS
ME/WE
OLD
DATA
1
1
0
0
MASK
0
1
0
1
,, ,,,,,,, ,,,,
,
,
,
INPUT
X
0
X
1
NEW
DATA
1
0
0
1
OLD
DATA
0
0
0
0
MASK
(REWRITE)
0
1
0
1
INPUT
X
1
X
1
NEW
DATA
0
ADDRESS 0
ADDRESS 1
X = NOT EFFECTIVE (DON’T CARE)
,
,
,
1
0
1
AFTER
DON’T CARE
UNDEFINED
Figure 1
AS42C4064 Bit MASKED-WRITE
REFRESH
The AS42C4064 883C supports
/
R
?
A
/
S-ONLY,
?
C
?
A
/
S-
BEFORE-/R
?
A
/
S, and HIDDEN types of refresh cycles. All
256 row address combinations must be accessed within
4ms. For the
/
C
?
A
/
S-BEFORE-/R
?
A
/
S REFRESH mode, the row
addresses are generated internally, and the user need not
supply them as must be done with
/
R
/
A
/
S-ONLY REFRESH.
/
T
/
R/(?O
/
E) must be HIGH when
/
R
?
A
/
S goes LOW for the
/
R
?
A
/
S-
ONLY and
/
C
/
A
/
S-BEFORE-/R
/
A
/
S types of refresh cycles. Any
READ, WRITE, or TRANSFER operation also refreshes the
DRAM row that is being accessed.
AS42C4064 883C
REV. 3/97
DS000013
3-5
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
.
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
