SRAM
Austin Semiconductor, Inc.
512K x 8 SRAM
Ultra Low Power SRAM
AVAILABLE AS MILITARY
SPECIFICATION
• SMD 5962-95613
• MIL STD-883
1
1,2
AS5C4009(LL)
PIN ASSIGNMENT
(Top View)
32-Pin DIP, 32-Pin SOJ
& 32-Pin TSOP
FEATURES
• Ultra Low Power with 2V Data Retention
(0.2mW MAX worst case Power-down standby)
• Fully Static, No Clocks
• Single +5V ±10% power supply
• Easy memory expansion with CE\ and OE\ options
• All inputs and outputs are TTL-compatible
• Three state outputs
• Operating temperature range:
Ceramic -55
o
C to +125
o
C & -40
o
C to +85
o
C
Plastic
-40
o
C to +85
o
C
3
1. Not applicable to plastic package
2. Applies to CW package only.
3. Contact factory for -55
o
C to +125
o
C
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
A17
WE\
A13
A8
A9
A11
OE\
A10
CE\
I/08
I/07
I/06
I/05
I/04
OPTIONS
MARKING
• Timing
55ns access
-55
4
70ns access
-70
85ns access
-85
100ns access
-100
• Packages
Ceramic Dip (600 mil)
CW
5
Ceramic SOJ
ECJ
Plastic TSOP
DG
•
Options
2V data retention/very low power LL
I/01
I/02
I/03
Vss
No. 112
No. 502
No. 1002
GENERAL DESCRIPTION
The AS5C4009LL is organized as 524,288 x 8 SRAM utilizing a
special ultra low power design process. ASI’s pinout adheres to the
JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32
pin version allows for easy upgrades from the 1 meg SRAM design.
For flexibility in memory applications, ASI offers chip enable (CE\)
and output enable (OE\) capabilities. These features can place the
outputs in High-Z for additional flexibility in system design.
This devices operates from a single +5V power supply and all
inputs and outputs are fully TTL-compatible.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW. The device offers a re-
duced power standby mode when disabled, by lowering VCC to 2V and
maintaining CE\ = 2V. This allows system designers to meet ultra low
standby power requirements.
4. For DG package, contact factory
5. Contact Factory
NOTE:
Not all combinations of operating temperature, speed, data retention and low power are
necessarily available. Please contact the factory for availability of specific part number
combinations.
Pin Name
Function
WE\
Write Enable Input
CE\
Chip Select Input
OE\
Output Enable Input
A0 - A18 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
Vcc
Power
Vss
Ground
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS5C4009(LL)
Rev. 4.1 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
Clk. gen.
Precharge circuit
AS5C4009(LL)
A18
A16
A14
A12
A7
A6
A5
A4
A1
A0
Row
select
Memory Array
1024 rows
512 x 8 columns
I/O
1
I/O
8
Data
cont
I/O Circuit
Column Select
Data
cont
A9
A8
A13
A17 A15
A10 A11
A3
A2
CE\
WE\
OE\
Control
logic
AS5C4009(LL)
Rev. 4.1 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss...................-.5V to +7.0V
Voltage on any pin Relative to Vss..........................-.5V to +7.0V
Storage Temperature ....................................-65°C to +150°C
Operating Temperature Range.............................-55
o
C to +125
o
C
Soldering Temperature Range...............................................260
o
C
Maximum Junction Temperature**....................................+150°C
Power Dissipation...................................................................1.0W
AS5C4009(LL)
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
** Junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
A
< 125
o
C; Vcc = 5V +10%)
PARAMETER/CONDITION
Input Leakage Current (V
IN
= V
SS
to V
CC
)
Output Leakage Current
(CE\=V
IH
or OE\=V
IH
or WE\=V
IL
, V
IO
=V
SS
to V
CC
)
Output Low Voltage (I
OL
= 2.1mA)
Output High Voltage (I
OH
= -1.0 mA)
Supply Voltage
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
I
LI
I
LO
V
OL
V
OH
V
CC
V
IH
V
IL
MIN
-5
-5
--
2.4
4.5
2.2
-0.5
MAX
5
5
0.4
--
5.5
Vcc +0.5
0.8
UNITS
µΑ
µΑ
V
V
V
V
V
15
15
15
1, 15
2, 15
NOTES
PARAMETER
Power Supply Current:
Operating
CONDITIONS
Cycle Time = Min., 100%
Duty Cycle, I
IO
= 0mA,
CE\ = V
IL
, V
IN
= V
IH
or V
IL
TTL
CE\ = V
IH
,
Other inputs = V
IL
or V
IH
CE\ = Vcc -0.2V,
Other inputs = 0 ~ Vcc
SYM
I
cc1
-55
100
MAX
-70
-85
90
80
-100 UNITS NOTES
70
mA
3
I
SB
6
6
6
6
mA
Power Supply Current:
Standby
CMOS
I
SB1
0.75
0.75
0.75
0.75
mA
AS5C4009(LL)
Rev. 4.1 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capactiance
CONDITIONS
o
T
A
= 25 C, f = 1MHz
V
CC
= 5V
AS5C4009(LL)
SYMBOL
V
IN
=0V
V
IO
=0V
C
IN
C
IO
MAXIMUM
8
10
UNITS
pF
pF
NOTES
4
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55
o
C < T
A
< 125
o
C; Vcc = 5V +10%)
DESCRIPTION
READ Cycle
READ cycle Time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
Output Enable access time
Output Enable to output in Low-Z
Output disable to output in High-Z
WRITE Cycle
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
SYM
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP1
t
DS
t
DH
t
LZWE
t
HZWE
-55
MIN MAX
55
55
55
10
10
20
0
55
30
5
20
55
50
50
0
0
50
30
0
5
25
-70
MIN MAX
70
70
70
10
10
25
0
70
35
5
25
70
60
60
0
0
60
30
0
5
25
-85
MIN MAX
85
85
85
10
10
30
0
85
40
5
30
85
70
70
0
0
70
35
0
5
30
-100
MIN MAX UNITS NOTES
100
100
100
10
10
30
0
100
45
5
30
100
80
80
0
0
80
40
0
5
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4,6
4,6
4,6
4,6
4,6
4,6
4
4
AS5C4009(LL)
Rev. 4.1 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
AS5C4009(LL)
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 3ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load ......................................... See Figures 1
Q
50
167 ohms
ohms
1.73V
C
C=30pF
= 100pF
Fig. 1 Output Load Equivalent
NOTES
1.
2.
3.
4.
5.
6.
Overshoot: Vcc +3.0V for pulse width < 20ms.
Undershoot: -3V for pulse width < 20ms.
I
CC
is dependent on output loading and cycle rates.
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
At any given temperature and voltage condition,
t
HZCE
is less than
t
LZCE
, and
t
HZWE
is less than
t
LZWE
.
WE\ is HIGH for READ cycle.
Device is continuously selected. Chip enables and
output enables are held in their active state.
Address valid prior to, or coincident with, latest
10.
11.
12.
13.
14.
occurring chip enable.
RC = Read Cycle Time.
Chip enable and write enable can initiate and
terminate a WRITE cycle.
Output enable (OE\) is inactive (HIGH).
Output enable (OE\) is active (LOW).
ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
All voltage referenced to Vss (GND).
t
7.
8.
9.
15.
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTION
V
CC
for Retention Data
Data Retention Current
V
IN
> (V
CC
- 0.2V)
Chip Deselect to Data
Retention Time
Operation Recovery Time
V
CC
= 3V
I
CCDR
t
CDR
t
R
0
5
200
CONDITIONS
CE\ > (V
CC
- 0.2V)
V
CC
= 2V
SYMBOL
V
DR
I
CCDR
MIN
2
MAX
100
UNITS
V
µA
µA
ns
ms
4
4, 10
NOTES
AS5C4009(LL)
Rev. 4.1 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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