gmZRX1 Data Sheet
Document History:
Revision
DAT-0025-A
DAT-0025-B
DAT-0025-C
Internal Release
First Public Release
Updated Pin Descriptions (page 5)
Deleted English Units (page 39)
Corrected Ordering Information (page 40)
DAT-0025-D
C0025-DAT-01E
Minor corrections in Table 2
December 1999
Description
Date
September 1999
October 1999
November 1999
This Datasheet Revision includes information April 2000
specific only to gmZRX1 Silicon Revision BD.
For applications which use earlier releases of
gmZRX1 silicon, users should refer to gmZRX1
Product Notices C0025-PRN-01B (re AB) and
C0025-PRN-02A (re BC).
The following sections have been revised:
3.1: page 6
5.1: page 14 (2 places)
5.8.1: pages 30 and 33
April 2000
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C0025-DAT-01E
gmZRX1 Data Sheet
Related Documents:
Doc Number
C0025-PRN-01B
C0025-PRN-02A
C0025-DSR-01B
Title
Date
GmZRX1 Product Notice: Differences Between April 2000
Silicon Revision AB and BC
GmZRX1 Product Notice: Differences Between February 2000
Silicon Revision BC and BD
GmZRX1 Register Programming Guide
April 2000
Copyright 2000
Genesis Microchip Inc.
All Rights Reserved
Genesis Microchip Inc. reserves the right to change or modify the information contained herein without
notice. It is the customer’s responsibility to ensure he/she has the most recent revision of the document.
Genesis Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any
errors or omissions which may appear in this document.
April 2000
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C0025-DAT-01E
gmZRX1 Data Sheet
TABLE OF CONTENTS
1.
2.
3.
4.
OVERVIEW ............................................................................................................................. 1
FEATURES & APPLICATIONS .............................................................................................. 2
PINOUT................................................................................................................................... 4
3.1
4.1
4.2
4.3
4.4
4.5
4.6
P
IN
D
ESCRIPTION
.................................................................................................................. 5
N
ATIVE
M
ODE
..................................................................................................................... 11
S
LOW
DCLK M
ODE
............................................................................................................ 11
E
XPANSION
M
ODE
.............................................................................................................. 12
D
OWNSCALING
M
ODE
......................................................................................................... 12
D
ESTINATION
S
TAND
A
LONE
M
ODE
..................................................................................... 12
I
NPUT
V
IDEO
M
ODE
S
UPPORT
............................................................................................. 12
OPERATING MODES........................................................................................................... 11
5.
FUNCTIONAL BLOCK DESCRIPTION................................................................................ 13
5.1 TMDS R
ECEIVER
B
LOCK
.................................................................................................... 14
5.2 I
NPUT
C
APTURE
/T
IMING
M
EASUREMENT
B
LOCKS
................................................................. 15
5.2.1. Input Capture Block.................................................................................................. 15
5.2.2. Input Timing Measurement Block............................................................................. 16
5.3 C
LOCK
S
YNTHESIZING
B
LOCK
............................................................................................. 18
5.4 D
ATA
P
ATH
......................................................................................................................... 19
5.5 G
AMMA
T
ABLE
.................................................................................................................... 20
5.5.1. Expander Interpolator............................................................................................... 20
5.5.2. RGB Offset ............................................................................................................... 20
5.5.3. Panel Data Dither ..................................................................................................... 20
5.5.4. Panel Background Color .......................................................................................... 20
5.6 P
ANEL
I
NTERFACE
............................................................................................................... 21
5.6.1. TFT Panel Interface Timing Specification ................................................................ 21
5.6.2. TFT LCD Power Sequencer ..................................................................................... 24
5.6.3. Panel Interface Drive Strength ................................................................................ f26
5.7 H
OST
I
NTERFACE
................................................................................................................ 27
5.7.1. Host interface pin connection ................................................................................... 27
5.7.2. gmZRX1 Serial Communication Protocol................................................................. 27
5.8 OSD (O
N
-S
CREEN
D
ISPLAY
) C
ONTROL
............................................................................... 30
5.8.1. On-Chip OSD ........................................................................................................... 30
5.8.2. External OSD Support.............................................................................................. 34
5.9 TCLK I
NPUT
....................................................................................................................... 36
5.10
P
OWER
D
OWN
M
ODE
..................................................................................................... 37
6.
7.
8.
ELECTRICAL CHARACTERISTICS .................................................................................... 38
MECHANICAL SPECIFICATIONS ....................................................................................... 39
ORDERING INFORMATION................................................................................................. 40
April 2000
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C0025-DAT-01E
gmZRX1 Data Sheet
TABLE OF FIGURES
F
IGURE
1: S
INGLE
-C
HIP
S
OLUTION FOR
L
OW
C
OST
F
LAT
P
ANEL
D
IGITAL
I
NTERFACE
M
ONITOR
..................... 3
F
IGURE
2:
GM
ZRX1 P
INOUT
............................................................................................................................ 4
F
IGURE
3:
GM
ZRX1 B
LOCK
D
IAGRAM
.......................................................................................................... 13
F
IGURE
4: C
APTURE
W
INDOW
....................................................................................................................... 16
F
IGURE
5: C
LOCK
S
YNTHESIZING
B
LOCK
D
IAGRAM
...................................................................................... 18
F
IGURE
6: D
ATA
P
ATH
................................................................................................................................... 19
F
IGURE
7: TFT P
ANEL
I
NTERFACE
T
IMING
(
ONE PIXEL PER CLOCK
) .............................................................. 23
F
IGURE
8: TFT P
ANEL
I
NTERFACE
D
ATA
L
ATCH
T
IMING
.............................................................................. 24
F
IGURE
9: S
ERIAL
C
OMMUNICATION
T
IMING
D
IAGRAM
................................................................................. 28
F
IGURE
10: S
ERIAL
H
OST
I
NTERFACE
D
ATA
T
RANSFER
F
ORMAT
.................................................................. 29
F
IGURE
11: O
N
-C
HIP
OSD W
INDOW
L
OCATION
............................................................................................ 32
F
IGURE
12:
GM
ZRX1 O
N
-
CHIP
F
ONTS IN
ROM............................................................................................. 33
F
IGURE
13: E
XTERNAL
OSD I
NTERFACE
D
ATA
L
ATCH
T
IMING
..................................................................... 35
April 2000
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C0025-DAT-01E