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MT48LC2M32B2B5-5: 产品描述Synchronous DRAM, 2MX32, 4.5ns, CMOS, PBGA90,; 产品类别存储存储; 文件大小2MB，共66页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/; 标准

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MT48LC2M32B2B5-5概述

Synchronous DRAM, 2MX32, 4.5ns, CMOS, PBGA90,

MT48LC2M32B2B5-5规格参数

参数名称	属性值
是否Rohs认证	符合
包装说明	FBGA, BGA90,9X15,32
Reach Compliance Code	compliant
最长访问时间	4.5 ns
最大时钟频率 (fCLK)	200 MHz
I/O 类型	COMMON
交错的突发长度	1,2,4,8
JESD-30 代码	R-PBGA-B90
内存密度	67108864 bit
内存集成电路类型	SYNCHRONOUS DRAM
内存宽度	32
端子数量	90
字数	2097152 words
字数代码	2000000
最高工作温度	70 °C
最低工作温度
组织	2MX32
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	FBGA
封装等效代码	BGA90,9X15,32
封装形状	RECTANGULAR
封装形式	GRID ARRAY, FINE PITCH
电源	3.3 V
认证状态	Not Qualified
刷新周期	4096
连续突发长度	1,2,4,8,FP
最大待机电流	0.002 A
最大压摆率	0.28 mA
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
Base Number Matches	1

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64Mb: x32 SDRAM

Features

Synchronous DRAM

MT48LC2M32B2 – 512K x 32 x 4 banks

For the latest data sheet, refer to Micron’s Web site: www.micron.com/sdram

Features

• PC100 functionality

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal pipelined operation; column address can be

changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge,

and auto refresh modes

• Self refresh mode

• 64ms, 4,096-cycle refresh (15.6µs/row)

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

• Supports CAS latency of 1, 2, and 3

Table 1:

Address Table

2 Meg x 32

Configuration

Refresh count

Row addressing

Bank addressing

Column addressing

512K x 32 x 4 banks

2K (A0–A10)

4 (BA0, BA1)

256 (A0–A7)

Table 2:

Key Timing Parameters

CL = CAS (READ) latency

Access

Time

CL = 3

4.5ns

5ns

5.5ns

Speed

Grade

-5

-55

-6

-7

Clock

Frequency

200 MHz

183 MHz

166 MHz

143 MHz

Setup

Time

1.5ns

2ns

Hold

Time

1ns

Options

• Configuration

2 Meg x 32 (512K x 32 x 4 banks)

• Plastic package - OCPL

86-pin TSOP (400 mil)

86-pin TSOP (400 mil) lead-free

90-ball VFBGA (8mm x 13mm) lead-free

• Timing (cycle time)

5ns (200 MHz)

5.5ns (183 MHz)

6ns (166 MHz)

7ns (143 MHz)

• Die rev

• Operating temperature range

Commercial (0° to +70°C)

Extended (–40°C to +85°C)

Notes: 1. Off-center parting line.

2. Available on -6 and -7.

Part Number Example:

Marking

2M32B2

-5

-55

-6

-7

None

Table 3:

64Mb (x32) SDRAM Part Number

Architecture

2 Meg x 32

Part Number

MT48LC2M32B2TG

MT48LC2M32B2P

MT48LC2M32B2B5

MT48LC2M32B2P-7:G

PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5

64MSDRAMx32_1.fm - Rev. J 2/06 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

64Mb: x32 SDRAM

General Description

The Micron

64Mb SDRAM is a high-speed CMOS, dynamic random-access memory

containing 67,108,864-bits. It is internally configured as a quad-bank DRAM with a

synchronous interface (all signals are registered on the positive edge of the clock signal,

CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32

bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select

the bank, A0–A10 select the row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8

locations, or the full page, with a burst terminate option. An auto precharge function

may be enabled to provide a self-timed row precharge that is initiated at the end of the

burst sequence.

The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-

tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while accessing one of the other three banks

will hide the precharge cycles and provide seamless, high-speed, random-access

operation.

The 64Mb SDRAM is designed to operate in 3.3V, low-power memory systems. An auto

refresh mode is provided, along with a power-saving, power-down mode. All inputs and

outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks to hide precharge time and

the capability to randomly change column addresses on each clock cycle during a burst

access.

PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5

64MSDRAMx32_1.fm - Rev. J 2/06 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

64Mb: x32 SDRAM

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Pin/Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Burst Read/Single Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5

64MSDRAMx32TOC.fm - Rev. J 2/06 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT48LC2M32B2B5-5相似产品对比

	MT48LC2M32B2B5-5	MT48LC2M32B2B5-6IT	MT48LC2M32B2B5-55
描述	Synchronous DRAM, 2MX32, 4.5ns, CMOS, PBGA90,	Synchronous DRAM, 2MX32, 5.5ns, CMOS, PBGA90,	Synchronous DRAM, 2MX32, 5ns, CMOS, PBGA90,
是否Rohs认证	符合	符合	符合
包装说明	FBGA, BGA90,9X15,32	FBGA, BGA90,9X15,32	FBGA, BGA90,9X15,32
Reach Compliance Code	compliant	compliant	compliant
最长访问时间	4.5 ns	5.5 ns	5 ns
最大时钟频率 (fCLK)	200 MHz	166 MHz	182 MHz
I/O 类型	COMMON	COMMON	COMMON
交错的突发长度	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 代码	R-PBGA-B90	R-PBGA-B90	R-PBGA-B90
内存密度	67108864 bit	67108864 bit	67108864 bit
内存集成电路类型	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
内存宽度	32	32	32
端子数量	90	90	90
字数	2097152 words	2097152 words	2097152 words
字数代码	2000000	2000000	2000000
最高工作温度	70 °C	85 °C	70 °C
组织	2MX32	2MX32	2MX32
输出特性	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	FBGA	FBGA	FBGA
封装等效代码	BGA90,9X15,32	BGA90,9X15,32	BGA90,9X15,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH
电源	3.3 V	3.3 V	3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified
刷新周期	4096	4096	4096
连续突发长度	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
最大待机电流	0.002 A	0.002 A	0.002 A
最大压摆率	0.28 mA	0.225 mA	0.26 mA
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES
技术	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	INDUSTRIAL	COMMERCIAL
端子形式	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM
Base Number Matches	1	1	1

MT48LC2M32B2B5-5

MT48LC2M32B2B5-5概述

MT48LC2M32B2B5-5规格参数

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