CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE), an active LOW Output Enable (OE), and tri-state
drivers. These devices have an automatic power-down feature
that reduces power consumption by more than 65% when the
devices are deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O
0
through I/O
3
) is then written into the location
specified on the address pins (A
0
through A
17
).
Reading from the devices is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the four I/O pins.
The four input/output pins (I/O
0
through I/O
3
) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LOW).
The CY7C106D is available in a standard 400-mil-wide
Pb-Free SOJ; the CY7C1006D is available in a standard
300-mil-wide Pb-Free SOJ.
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
CE
OE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT BUFFER
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
I/O
3
SENSE AMPS
I/O
2
I/O
1
I/O
0
POWER
DOWN
512 x 512 x 4
ARRAY
V
CC
A
17
A
16
A
15
A
14
A
13
A
12
A
11
NC
I/O
3
I/O
2
I/O
1
I/O
0
WE
COLUMN
DECODER
CE
WE
OE
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
A
0
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
Cypress Semiconductor Corporation
Document #: 38-05459 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 11, 2005
PRELIMINARY
Selection Guide
CY7C106D-10
CY7C1006D-10
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
10
60
3
CY7C106D
CY7C1006D
CY7C106D-12
CY7C1006D-12
12
50
3
Document #: 38-05459 Rev. *C
Page 2 of 10
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
Relative to GND
[2]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State
[2]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
.................................–0.5V to V
CC
+ 0.5V
CY7C106D
CY7C1006D
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–45°C to +85°C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C106D-10
7C1006D-10
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
Description
Test Conditions
Min.
2.4
0.4
2.0
–0.5
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
–1
–1
V
CC
+ 0.3
0.8
+1
+1
–300
60
10
2.0
–0.5
–1
–1
Max.
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
7C106D-12
7C1006D-12
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
–300
50
10
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
Automatic CE
Max. V
CC
, CE > V
IH
,
Power-Down Current V
IN
> V
IH
or V
IN
< V
IL
,
—TTL Inputs
f = f
MAX
Automatic CE
Max. V
CC
, CE > V
CC
– 0.3V,
Power-Down Current V
IN
> V
CC
– 0.3V
—CMOS Inputs
or V
IN
< 0.3V, f=0
I
SB2
3
3
mA
Capacitance
[4]
Parameter
C
IN
: Addresses
C
IN
: Controls
C
OUT
Output Capacitance
Description
Input Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
7
10
10
Unit
pF
pF
pF
Thermal Resistance
[4]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
[4]
Thermal Resistance
(Junction to Case)
[4]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
All-Packages
TBD
TBD
Unit
°C/W
°C/W
Notes:
2. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 2V for pulse durations of less than 20 ns.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05459 Rev. *C
Page 3 of 10
PRELIMINARY
AC Test Loads and Waveforms
10-ns Device
OUTPUT
50
Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
12 -ns Devices
R1 480
Ω
5V
CY7C106D
CY7C1006D
ALL INPUT PULSES
Z = 50Ω
3.0V
90%
90%
10%
Fall Time < 1V/ns
30 pF*
GND
Rise Time < 1V/ns
10%
1.5V
(a)
High-Z Characteristics
R1 480
Ω
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
30 pF
R2
255
Ω
5 pF
R2
255
Ω
(b)
Equivalent to:
(c)
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Switching Characteristics
Over the Operating Range
[5]
7C106D-10
7C1006D-10
Parameter
Read Cycle
t
power[6]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[7, 8]
CE LOW to Low Z
[8]
CE HIGH to High Z
[7, 8]
7C106D-12
7C1006D-12
Min.
100
12
Max.
Unit
µs
ns
12
3
12
6
0
5
6
3
5
6
0
12
12
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
100
10
Max.
10
3
10
5
0
3
0
10
10
8
7
0
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Write Cycle
[9, 10]
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. t
POWER
gives the minimum amount of time that the power supply should be at typical V
CC
values until the first memory access can be performed.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±200
mV from steady-state voltage.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05459 Rev. *C
Page 4 of 10
PRELIMINARY
Switching Characteristics
Over the Operating Range
[5]
7C106D-10
7C1006D-10
Parameter
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Description
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[8]
WE LOW to High
Z
[7, 8]
Min.
0
7
6
0
3
6
Max.
0
10
7
0
2
CY7C106D
CY7C1006D
7C106D-12
7C1006D-12
Min.
Max.
Unit
ns
ns
ns
ns
ns
6
ns
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
t
CDR[4]
t
R[11, 12]
Description
V
CC
for Data Retention
Non-L, Com’l / Ind’l V
CC
= V
DR
= 2.0V,
L-Version Only CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
Chip Deselect to Data Retention Time
V
IN
< 0.3V
Operation Recovery Time
Data Retention Current
Conditions
Min.
2.0
3
1.2
0
t
RC
Max.
Unit
V
mA
mA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
4.5V
t
CDR
CE
V
DR
> 2V
4.5V
t
R
Switching Waveforms
Read Cycle No.1
[13, 14]
1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DA TA VALID
DATA VALID
Notes:
11. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50
µs
or stable at V
CC(min.)
> 50
µs.
12. t
r
< 3 ns for all speeds.
13. Device is continuously selected, OE and CE = V
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